NCP1280
http://onsemi.com
16
Figure 34. Soft−Start Timing Diagram
OUT1
OUT2
V
SS
Oscillator
Ramp
If the soft−start period is too long, V
AUX
will discharge to
7 V before the converter output is completely in regulation
causing the outputs to be disabled. If the converter output is
not completely discharged when the outputs are re−enabled,
the converter will eventually reach regulation exhibiting a
non−monotonic startup behavior. But, if the converter
output is completely discharged when the outputs are
re−enabled, the cycle may repeat and the converter will not
start.
In the event of an UV, OV, or cycle skip fault, the soft−start
capacitor is discharged. Once the fault is removed, a
soft−start cycle commences. The soft−start steady state
voltage is approximately 4.1 V.
Control Outputs
The NCP1280 has two in−phase control outputs, OUT1
and OUT2, with adjustable overlap delay (t
D
). OUT2
precedes OUT1 during a low to high transition and OUT1
precedes OUT2 at any high to low transition. Figure 35
shows the relationship between OUT1 and OUT2.
Figure 35. Control Outputs Timing Diagram
t
D
(Trailing)t
D
(Leading)
OUT1
OUT2
Generally, OUT1 controls the main switching element.
Output 2, once inverted, can control a synchronous rectifier.
The overlap delay prevents simultaneous conduction.
Output 2 can also be used to control an active clamp reset.
Once V
AUX
reaches 11 V, the internal startup circuit is
disabled and the One Shot Pulse Generator is enabled. If no
faults are present, the outputs turn ON. Otherwise, the
outputs remain OFF until the fault is removed and V
AUX
reaches 11 V again.
The control outputs are biased from V
AUX
. The outputs
can supply up to 10 mA each and their high state voltage is
usually 0.2 V below V
AUX
. Therefore, the auxiliary supply
voltage should not exceed the maximum input voltage of the
driver stage.
If the control outputs need to drive a large capacitive load,
a driver should be used between the NCP1280 and the load.
ON Semiconductor’s MC33152 is a good selection for an
integrated driver. Figures 27 and 28 shows the relationship
between the output’s rise and fall times vs capacitive load.
Time Delay
The overlap delay between the outputs is set connecting
a resistor (R
D
) between the t
D
and V
REF
pins. A minimum
overlap delay of 80 ns is obtained when R
D
is 60 k. If R
D
is not present, the delay is 200 ns.
The output duty cycle can be adjusted from 0% to 85%
selecting appropriate values of R
FF
and V
DC(inv)
. It should
be noted that the overlap delay may cause OUT2 to reach
100% duty cycle. Therefore, if OUT2 is used, the maximum
duty cycle of OUT2 needs to be kept below 100%. The
maximum overlap delay, t
D(max)
, depends on the maximum
duty cycle and frequency of operation. The maximum
overlap delay is calculated using the equation below.
t
D(max)
v
(1 * DC)
2
ƒ
For example, if the converter operates at a frequency of
300 kHz with a maximum duty cycle of 80%, the maximum
allowed overlap delay is 333 ns. However, this is a
theoretical limit and variations over the complete operating
range should be considered when selecting the overlap
delay.
