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841202BK-245LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
DATA SHEET
ICS841202BK-245 REVISION A AUGUST 20, 2013 1 ©2013 Integrated Device Technology, Inc.
Crystal-to-HCSL Clock Synthesizer
w/Spread Spectrum
ICS841202-245
Phase
Detector
VCO
Feedback Divider
÷20
Spread Spectrum
Control
OSC
0 0 PLL Bypass
0 1 ÷5
1 0 ÷4
1 1 ÷2
Q0
nQ0
Q1
nQ1
OE
XTAL_IN
XTAL_OUT
SSC[1:0]
IREF
FSEL[1:0]
Pullup
Default = 100MHz
25MHz
Pullup:Pullup
Pulldown:Pullup
2
2
General Description
The ICS841202-245 is a two output clock synthesizer optimized to
generate low jitter with or without spread spectrum modulation.
Spread type and amount can be configured via the SSC control pins.
Using a 25MHz, 12pF parallel resonant crystal, the device will
generate HCSL clocks at either 25MHz, 100MHz, 125MHz or
250MHz. The ICS841202-245 uses a low jitter VCO and is packaged
in a 32-pin VFQFN pa
ckage.
Features
• Two differential HCSL output pairs at: 100MHz, 125MHz or
250MHz
• HCSL outputs can be terminated to drive LVDS loads up to
175MHz
• 25MHz crystal interface
• Supports the following output frequencies: 25MHz, 100MHz,
125MHz or 250MHz
• Supports SSC downspread, centerspread and no spread options
• Cycle-to-cycle jitter: 55ps (maximum)
• Period jitter, RMS: 4.15ps (maximum)
• Full 3.3V operating supply mode
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) packaging
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VDD
VDD
nc
nc
V
DD
nc
FSEL0
nc
nc
IREF
GND
nc
nc
SSC1
nc
GND
FSEL1
SSC0
V
DD
nc
XTAL_IN
XTAL_OUT
OE
GND
nQ0
GND
GND
V
DDA
VDD
Q1
nQ1
Q0
Block Diagram
Pin Assignment
ICS841202-245
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm ePad Size
K Package
Top View
ICS841202-245 Data Sheet CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
ICS841202BK-245 REVISION A AUGUST 20, 2013 2 ©2013 Integrated Device Technology, Inc.
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Tables
Table 3A. FSEL[1:0] Function Table Table 3B. SSC[1:0] Function Table
Number Name Type Description
1, 2, 5, 11, 27 V
DD
Power Core supply pins.
3, 4, 6, 8, 12, 18,
20, 21, 24
nc Unused No connect.
7FSEL0 InputPullupOutput frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
9FSEL1 InputPulldown Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
10,
19
SSC0,
SSC1
InputPullup Spread spectrum control pins. See Table 3B. LVCMOS/LVTTL interface levels.
13,
14
XTAL_IN,
XTAL_OUT
Inpu
t
Parallel resonant crystal interface. XTAL_IN is the input, XTAL_OUT is the
output. (PLL reference.)
15 OE InputPullup
Output enable pin. Logic HIGH, outputs are enabled. Logic LOW, outputs are in
an High-Impedance state. LVCMOS/LVTTL interface levels.
16, 17, 22, 29, 30 GND Power Power supply ground.
23 IREF Power
HCSL current reference resistor output. An external fixed precision resistor
(475) from this pin to ground provides a reference current used for differential
current-mode Qx, nQx clock outputs.
25, 26 nQ1, Q1 Output Differential output pair. HCSL interface levels.
28 V
DDA
Power Analog supply pin.
31, 32 nQ0, Q0 Output Differential output pair. HCSL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance OE, FSEL[1:0], SSC[1:0] 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
Inputs
Output
Divided by
Outputs
FSEL1 FSEL0 Q[0:1], nQ[0:1]
0 0 PLL Bypass 25MHz
0 1 5 100MHz (default)
10 4 125MHz
11 2 250MHz
Inputs
Spread%SSC1 SSC0
0 0 Center ± 0.3
0 1 Down -0.6
1 0 Down -0.9
11No Spread (default)
ICS841202-245 Data Sheet CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
ICS841202BK-245 REVISION A AUGUST 20, 2013 3 ©2013 Integrated Device Technology, Inc.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Table 5. Crystal Characteristics
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
XTAL_IN
Other Inputs
0V to V
DD
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
43.4C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDA
Analog Supply Voltage V
DD
– 0.2 3.3 V
DD
V
I
DD
Power Supply Current 130 158 mA
I
DDA
Analog Supply Current 15 20 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input
High Current
FSEL1 V
DD
= V
IN
= 3.465V 150 μA
SSC0, SSC1,
FSEL0, OE
V
DD
= V
IN
= 3.465V 5 μA
I
IL
Input
Low Current
FSEL1 V
DD
= 3.465V, V
IN
= 0V -5 μA
SSC0, SSC1,
FSEL0, OE
V
DD
= 3.465V, V
IN
= 0V -150 μA
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 25 MHz
Equivalent Series Resistance (ESR) 50
Load Capacitance (C
L
) 12
pF
Shunt Capacitance 7pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

841202BK-245LF

Mfr. #:
Buy 841202BK-245LF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Crystal-to-HCSL Clock Synth w/Spread
Lifecycle:
New from this manufacturer.
Delivery:
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