ICS841202-245 Data Sheet CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
ICS841202BK-245 REVISION A AUGUST 20, 2013 10 ©2013 Integrated Device Technology, Inc.
Recommended Termination
Figure 3A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express and HCSL output types.
All traces should be 50 impedance single-ended or 100
differential.
Figure 3A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 3B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0 to 33. All trace
s should be 50
impedance single-ended or 100 differential.
Figure 3B. Recommended Termination (where a point-to-point connection can be used)
0-0.2"
PCI Express
L1
L1
1-14"
Driver
Rs
0.5" Max
L3
L4
L2
L2
49.9 +/- 5%
22 to 33 +/-5%
Rt
L3
L4
L5
0.5 - 3.5"
L5
Connector
PCI Express
Add-in Card
PCI Express
0-0.2"
PCI Express
0-0.2"0-18"
L1
L1
Rs
Driver
0.5" Max
L3
L3
L2
L2
49.9 +/- 5%
0 to 33
0 to 33
Rt
ICS841202-245 Data Sheet CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
ICS841202BK-245 REVISION A AUGUST 20, 2013 11 ©2013 Integrated Device Technology, Inc.
Application Schematic Example
Figure 4 (next page) shows an example of ICS841202-245
application schematic. The schematic example focuses on functional
connections and is not configuration specific. Refer to the pin
description and functional tables in the datasheet to ensure that the
logic control inpu ts are properly set.
A 12pF parallel resonant 25MHz crystal is used. For this device, the
cryst
al load capacitors are required for proper operation. The load
capacitance, C1 = C2 = 15pF, are recommended for frequency
accuracy. Depending on the variation of the parasitic stray capacity
of the printed circuit board traces between the crystal and the
XTAL_IN and XTAL_OUT pins, the values of C1 and C2 might require
a slight adjustment to optimize the frequency accuracy. Cry
stals with
other load capacitance specifications can be used, but this will
require adjusting C1 and C2. When designing the circuit board,
return the capacitors to ground though a single point contact close to
the package.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random nois
e. To achieve optimum jitter performance,
power supply isolation is required. The ICS841202-245 provides
separate power supplies to isolate any high switching noise from
coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter s
hould be placed on the
device side. The other components can be on the opposite side of the
PCB. Power supply filter recommendations are a general guideline to
be used for reducing external noise from coupling into the devices
The filter performance is designed for a wide range of noise
frequencies. This low-pass filter starts to attenuate noise at
approximately 10kHz. a specific frequency noise component is
known, su
ch as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
ICS841202-245 Data Sheet CRYSTAL-TO-HCSL CLOCK SYNTHESIZER
ICS841202BK-245 REVISION A AUGUST 20, 2013 12 ©2013 Integrated Device Technology, Inc.
Figure 5. ICS841202-245 Schematic Example
U1
FSEL0
7
FSEL1
9
SSC0
10
SSC1
19
XT AL _I N
13
XT AL _O U T
14
OE
15
IREF
23
nc
3
nc
4
nc
6
nc
8
nc
12
nc
18
nc
20
nc
21
nc
24
nQ1
25
Q1
26
nQ0
31
Q0
32
VDD
1
VDD
2
VDD
5
VDD
11
VDD
27
VDDA
28
GN D
16
GND
17
GN D
22
GND
29
GN D
30
X1
1
3
2 4
25 M Hz
(12p f)
XT AL_O U T
XTAL_IN
C2
15 pF
C1
15pF
Fox 32 5BS crys tal
R1
475
FSEL1
FSEL0
OE
SSC1
SSC0
Zo = 50
Zo = 50
Q0
0 " to 18"
0 .5" t o 3.5 "1" to 1 4"
R2 33
R3 33
PCI Express Add-In Card
Optional
nQ0
PCI Express
Point-to-Point
Connection
R4
50
Zo = 50
Zo = 50
R5
50
R6 33
Zo = 50
R7
50
Zo = 50
R8
50
R9 33
HCSL_Receiv e r
+
-
H CSL_R ece iv er
+
-
nQ1
Q1
VDD
To Logic
Input
pins
VDD
RU2
Not Install
RU 1
1K
RD2
1K
To Logic
Input
pins
RD 1
Not I ns tall
Set Logic
Input to '1'
Logic Control Input Examples
Set Logic
Input to '0'
C3
10u F
C4
0. 1uF
3. 3V
C5
10uF
FB 1
BLM18BB221SN 1
12
R10 10
C6
0. 1uF
C7
0 .1uF
Place each 0.1uF bypass cap directly
adjacent to its corresponding VDD or
VDDA pin.
VDDA
VD D
C8
0. 1uF
C9
0. 1uF
C10
0. 1uF

841202BK-245LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Crystal-to-HCSL Clock Synth w/Spread
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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