NXP Semiconductors
MF1S70YYX_V1
MIFARE Classic EV1 4K - Mainstream contactless smart card IC for fast and easy solution development
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2017. All rights reserved.
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Date of release: 23 November 2017
Document identifier: MF1S70yyX_V1
Document number: 279332
Contents
1 General description ............................................ 1
1.1 Anticollision ........................................................ 1
1.2 Simple integration and user convenience .......... 1
1.3 Security and privacy .......................................... 1
1.4 Delivery options ................................................. 1
2 Features and benefits .........................................2
2.1 EEPROM ........................................................... 2
3 Applications .........................................................2
4 Quick reference data .......................................... 2
5 Ordering information .......................................... 3
6 Block diagram ..................................................... 3
7 Pinning information ............................................ 4
7.1 Pinning ............................................................... 4
8 Functional description ........................................4
8.1 Block description ............................................... 4
8.2 Communication principle ................................... 5
8.2.1 Request standard / all ....................................... 5
8.2.2 Anticollision loop ................................................ 5
8.2.3 Select card .........................................................5
8.2.4 Three pass authentication ................................. 5
8.2.5 Memory operations ............................................ 6
8.3 Data integrity ..................................................... 6
8.4 Three pass authentication sequence .................7
8.5 RF interface ....................................................... 7
8.6 Memory organization ......................................... 7
8.6.1 Manufacturer block ............................................ 8
8.6.2 Data blocks ........................................................9
8.6.2.1 Value blocks ...................................................... 9
8.6.3 Sector trailer .................................................... 10
8.7 Memory access ............................................... 10
8.7.1 Access conditions ............................................ 11
8.7.2 Access conditions for the sector trailer ............ 12
8.7.3 Access conditions for data blocks ................... 12
9 Command overview .......................................... 13
9.1 MIFARE Classic command overview ...............13
9.2 Timings ............................................................ 14
9.3 MIFARE Classic ACK and NAK .......................15
9.4 ATQA and SAK responses .............................. 16
10 UID Options and Handling ............................... 16
10.1 7-byte UID Operation .......................................16
10.1.1 Personalization Options ...................................16
10.1.2 Anti-collision and Selection ..............................18
10.1.3 Authentication .................................................. 18
10.2 4-byte UID Operation .......................................18
10.2.1 Anti-collision and Selection ..............................19
10.2.2 Authentication .................................................. 19
11 Load Modulation Strength Option ................... 19
12 MIFARE Classic commands .............................20
12.1 MIFARE Authentication ................................... 20
12.2 MIFARE Read ................................................. 21
12.3 MIFARE Write ..................................................22
12.4 MIFARE Increment, Decrement and Restore ...24
12.5 MIFARE Transfer .............................................25
13 Limiting values ..................................................26
14 Characteristics .................................................. 27
15 Wafer specification ........................................... 27
15.1 Fail die identification ........................................ 28
15.2 Package outline ............................................... 28
16 Bare die outline .................................................31
17 Abbreviations .................................................... 31
18 References ......................................................... 32
19 Revision history ................................................ 33
20 Legal information .............................................. 34
