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9ZXL1530BKLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
DATASHEET
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
9ZXL1530
IDT®
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 1
9ZXL1530 REV D 112015
Description
The 9ZXL1530 is a 15-output version of the Intel DB1900Z
Differential Buffer utilizing Low-Power HCSL (LP-HCSL)
outputs to reduce power consumption more than 50% from
the original IDT9ZX21501. It is suitable for PCI-Express
Gen1/2/3 or QPI/UPI applications, and uses a fixed external
feedback to maintain low drift for demanding QPI/UPI
applications.
Recommended Application
Buffer for Romley, Grantley and Purley Servers
Key Specifications
• Cycle-to-cycle jitter: < 50ps
• Output-to-output skew: <65ps
• Input-to-output delay: Fixed at 0 ps
• Input-to-output delay variation: <50ps
• Phase jitter: PCIe Gen3 < 1ps rms
• Phase jitter: QPI 9.6GB/s < 0.2ps rms
Features/Benefits
• Fixed feedback path; 0ps input-to-output delay
• 9 Selectable SMBus addresses; Multiple devices can
share same SMBus segment
• Separate VDDIO for outputs; allows maximum power
savings
• PLL or bypass mode; PLL can dejitter incoming clock
• Selectable PLL BW; minimizes jitter peaking in
downstream PLL's
• Spread spectrum compatible; tracks spreading input
clock for EMI reduction
• SMBus Interface; unused outputs can be disabled
• 100MHz & 133.33MHz PLL mode; Legacy QPI/UPI
support
• Differential outputs are Low/Low in power down;
Maximum power savings
Output Features
• 15 - LP-HCSL Differential Output Pairs
Block Diagram
Logic
DIF(14:0)
HIBW_BYPM_LOBW#
SMBDAT
SMBCLK
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
100M_133M#
Z-PLL
(SS Compatible)
FBOUT_NC
DIF_IN
DIF_IN#
9ZXL1530
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
IDT®
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 2
9ZXL1530 REV D 112015
Pin Configuration
Power Management Table
Power Connections
Functionality at Power-up (PLL mode)
PLL Operating Mode
Tri-Level Input Thresholds
GND
VDDIO
DIF_14 #
DIF_14
DIF_13#
DIF_13
VDD
GND
DIF_12 #
DIF_12
DIF_11#
DIF_11
GND
VDDIO
DIF_10#
DIF_10
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VD DA
1
48
VDDIO
GN DA
247
GND
100M_133M#
346
DI F_9#
HIBW_BYPM_LOBW#
4
45
DIF_9
CKPWRGD_PD#
544
DI F_8#
GND
643
DIF_8
VDDR
742
GND
DIF_IN
841
VDD
DIF_IN#
940
DI F_7#
SMB_A0_tri
10 39
DIF_7
SMBDAT
11 38
DI F_6#
SMBCLK
12 37
DIF_6
SMB_A1_tri
13 36
VDDIO
FBOUT_NC#
14 35
GND
FBOUT_NC
15 34
DI F_5#
GND
16 33
DIF_5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DIF_0
DIF_0#
VDDIO
GND
DIF_1
DIF_1#
DIF_2
DIF_2#
GND
VD D
DIF_3
DIF_3#
DIF_4
DIF_4#
VDDIO
GND
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldowm
9ZXL1530
Control Bits
CKPWRGD_PD#
DIF
_
IN/
DIF_IN#
SMB
us
EN bit
DIF
_x
/
DIF_x#
FBOUT
_
NC/
FBOUT_NC#
0 X X Low/Low Low/Low OFF
0 Low /Low Running ON
1 Running Running ON
Inputs
PLL State
1 Running
Outputs
VDD VDDIO GND
Pin N umbe
r
100M_133M#
DIF_IN
(MHz)
DIFx
(MHz)
1 100.00 DIF_IN
0 133.33 DIF_IN
HiBW_BypM_LoBW# Byte0, bit (7:6)
Low ( PLL Low BW) 00
Mid (Bypass) 01
High (PLL High BW) 11
NOTE: PLL is off in Bypass mode
Level Voltage
Low <0.8V
Mid 1.2<Vin<1.8V
High
Vin > 2.2V
9ZXL1530
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
IDT®
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 3
9ZXL1530 REV D 112015
Pin Descriptions
PIN # PIN NAME TYPE DESCRIPTION
1 VDDA PWR 3.3V power for the PLL core.
2 GNDA PWR Ground pin for the PLL core.
3 100M_133M# IN
3.3V Input to select operating frequency
See Functionality Table for Definition
4 HIBW_BYPM_LOBW# IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for D etails.
5CKPWRGD_PD# IN
Notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on
subsequent assertions. Low enters Power Down Mode.
6 GND PWR Ground pin.
7VDDR PWR
3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and
filtered appropriately.
8 DIF_IN IN 0.7 V Differential TRUE input
9 DIF_IN# IN 0.7 V Differential Com
p
lementar
y
In
p
ut
10 SMB_A0_tri IN
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9 SMBus
Addresses.
11 SMBDAT I/O Data
p
in of SMBUS circuitr
y
, 5V tolerant
12 SMBCLK IN Clock
p
in of SMBUS circuitr
y
, 5V tolerant
13 SMB_A1_tri IN
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9 SMBus
Addresses.
14 FBOUT_NC# OUT
Complementary half of differential feedback output. This pin should NOT be connected to anything outside t he
chi
p
. It exists to
p
rovide dela
y
p
ath match in
g
to
g
et 0
p
ro
p
a
g
ation d ela
y
.
15 FBOUT_NC OUT
True half of differential feedback output. This pin should NOT be connected to anything outside t he chip. It
exists to
p
rovide dela
y
p
ath matchin
g
to
g
et 0
p
ro
p
a
g
ation de la
y
.
16 GND PWR Ground
p
in.
17 DIF_0 OU
T
0.7V differential true clock out
p
ut
18 DIF_0# OUT 0.7V differential Complementary clock output
19 VDDIO PWR Power supply for differential outputs
20 GND PWR Ground pin.
21 DIF_1 OUT 0.7V differential true clock output
22 DIF_1# OUT 0.7V differential Complementary clock output
23 DIF_2 OUT 0.7V differential true clock output
24 DIF_2# OUT 0.7V differential Complementary clock output
25 GND PWR Ground pin.
26 VDD PWR Power supply, nominal 3.3V
27 DIF_3 OUT 0.7V differential true clock output
28 DIF_3# OUT 0.7V differential Complementary clock output
29 DIF_4 OUT 0.7V differential true clock output
30 DIF_4# OUT 0.7V differential Complementary clock output
31 VDDIO PWR Power supply for differential outputs
32 GND PWR Ground pin.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9ZXL1530BKLFT

Mfr. #:
Buy 9ZXL1530BKLFT
Manufacturer:
IDT
Description:
Clock Buffer HIGH PERF. ZDB
Lifecycle:
New from this manufacturer.
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