9ZXL1530
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
IDT®
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 10
9ZXL1530 REV D 112015
Test Loads
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Clock Periods–Differential Outputs with Spread Spectrum Enabled
Differential Output Terminations
DIF Zo (
)Rs (
)
100 33
85 27
Differential Zo,
10 inches
LP-HCSL
Differential
Output
9ZXL Differential Test Loads
Rs
Rs
2pF 2pF
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
100.00 9.94900 9.99900 10.0000 0 10.00100 10.05100 ns 1,2,3
133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4
SSC OFF
Center
Freq.
MHz
DIF
Measurement Window
Units Notes
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
99.75 9.94906 9.99906 10.02406 10.0250 6 10.02607 10.05107 10.10107 ns 1,2,3
133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4
Notes:
1
Guaranteed by design and characterization, not 100% tested in production.
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode
4
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
2
All Long Term Accuracy specifications are guaran teed with the assumption that the input clock complies with CK420BQ/CK410B+ accuracy
requirements (+/-100ppm). The 9ZXL1530 itself does not contribute to ppm error.
DIF
Notes
9ZXL1530
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
IDT®
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 11
9ZXL1530 REV D 112015
General SMBus Serial Interface Information
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
9ZXL1530
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
IDT®
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE 12
9ZXL1530 REV D 112015
9ZXL1530 SMBus Addressing
SMB_A(1:0)_tri A ddress (Rd/Wrt bit = 0) (Hex)
00 D8
0M DA
01 DE
M0 C2
MM C4
M1 C6
10 CA
1M CC
11 CE
SMBusTable: PLL Mode, and Frequency Select Re
g
ister
Pin # Name Control Function Type 0 1 Default
Bit 7
PLL Mode 1 PLL Operating Mode Rd back 1
R
Latch
Bit 6
PLL Mode 0 PLL Operating Mode Rd back 0
R
Latch
Bit 5
1
Bit 4
DIF_14_En Output Enable RW Low/Low Enable 1
Bit 3
DIF_13_En Output Enable RW Low/Low Enable 1
Bit 2
0
Bit 1
0
Bit 0
100M_133M# Fre
q
uenc
y
Select Readb ack
R
133MHz 100MHz
Latch
SMBusTable: Output Control Re
g
iste
r
Pin # Name Control Function Type 0 1 Default
Bit 7
DIF_5_En Output Enable RW Low/Low Enable 1
Bit 6
1
Bit 5
DIF_4_En Output Enable RW 1
Bit 4
DIF_3_En Output Enable RW 1
Bit 3
DIF_2_En Output Enable RW 1
Bit 2
DIF_1_En Out
p
ut Enable RW 1
Bit 1
DIF_0_En Out
p
ut Enable RW 1
Bit 0
1
SMBusTable: Output Control Registe
r
Pin # Name Control Function Type 0 1 Default
Bit 7
DIF_12_En Out
p
ut Enable RW Low/Low Enable 1
Bit 6
DIF_11_En Out
p
ut Enable RW 1
Bit 5
DIF_10_En Out
p
ut Enable RW 1
Bit 4
1
Bit 3
DIF_9_En Out
p
ut Enable RW 1
Bit 2
DIF_8_En Out
p
ut Enable RW 1
Bit 1
DIF_7_En Out
p
ut Enable RW 1
Bit 0
DIF_6_En Output Enable RW 1
SMBusTable: Reserved Re
g
ister
Pin # Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reserved
Reserved
Reserved
Reserved
39/40
45/46
3
Byte 1
43/44
Byte 2
39/40
Byte 0
4
4
61/62
59/60
21/22
17/18
55/56
37/38
29/30
29/30
23/24
53/54
49/50
Byte 3
See PLL Operating Mode
Readback Table
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Low/Low Enable
Reserved

9ZXL1530BKLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer HIGH PERF. ZDB
Lifecycle:
New from this manufacturer.
Delivery:
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