OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADF4360-7BCPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
ADF4360-7 Data Sheet
Rev. E | Page 18 of 28
Hardware Power-Up/Power-Down
If the device is powered down via the hardware (using the
CE pin) and powered up again without any change to the
N counter register during power-down, the device locks at the
correct frequency, because the device is already in the correct
frequency band. The lock time depends on the value of capaci-
tance on the C
N
pin, which is <10 ms for 10 µF capacitance. The
smaller capacitance of 440 nF on this pin enables lock times of
<600 µs.
The N counter value cannot be changed while the device is in
power-down, since the device may not lock to the correct
frequency on power-up. If it is updated, the correct program-
ming sequence for the device after power-up is the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the Initial Power-Up section.
Software Power-Up/Power-Down
If the device is powered down via the software (using the con-
trol latch) and powered up again without any change to the N
counter latch during power-down, the device locks at the cor-
rect frequency, because the device is already in the correct fre-
quency band. The lock time depends on the value of capaci-
tance on the C
N
pin, which is <10 ms for 10 µF capacitance. The
smaller capacitance of 440 nF on this pin enables lock times of
<600 µs.
The N counter value cannot be changed while the device is in
power-down, because the device may not lock to the correct
frequency on power-up. If it is updated, the correct program-
ming sequence for the device after power-up is to the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the Initial Power-Up section.
Data Sheet ADF4360-7
Rev. E | Page 19 of 28
CONTROL LATCH
With (C2, C1) = (0, 0), the control latch is programmed. Table 7
shows the input data format for programming the control latch.
Prescaler Value
In the ADF4360-7, P2 and P1 in the control latch set the pre-
scaler values.
Power-Down
DB21 (PD2) and DB20 (PD1) provide programmable powerdown
modes.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1, with
the condition that PD2 has been loaded with a 0. In the pro-
grammed synchronous power-down, the device power-down is
gated by the charge pump to prevent unwanted frequency
jumps. Once the power-down is enabled by writing a 1 into
Bit PD1 (on the condition that a 1 has also been loaded to PD2),
the device goes into power-down on the second rising edge of
the R counter output, after LE goes high. When the CE pin is
low, the device is immediately disabled regardless of the state of
PD1 or PD2.
When a power-down is activated (either synchronous or
asynchronous mode), the following events occur:
• All active dc current paths are removed.
• The R, N, and timeout counters are forced to their load
state conditions.
• The charge pump is forced into three-state mode.
• The digital lock detect circuitry is reset.
• The RF outputs are debiased to a high impedance state.
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading
and latching data.
Charge Pump Currents
CPI3, CPI2, and CPI1 in the ADF4360-7 determine
Current Setting 1.
CPI6, CPI5, and CPI4 determine Current Setting 2. See the
truth table in Table 7.
Output Power Level
Bits PL1 and PL2 set the output power level of the VCO. See the
truth table in Table 7.
Mute-Till-Lock Detect
DB11 of the control latch in the ADF4360-7 is the mute-till-
lock detect bit. This function, when enabled, ensures that the
RF outputs are not switched on until the PLL is locked.
CP Gain
DB10 of the control latch in the ADF4360-7 is the charge pump
gain bit. When it is programmed to 1, Current Setting 2 is used.
When it is programmed to 0, Current Setting 1 is used.
Charge Pump Three-State
This bit puts the charge pump into three-state mode when
programmed to a 1. It should be set to 0 for normal operation.
Phase Detector Polarity
The PDP bit in the ADF4360-7 sets the phase detector polarity.
The positive setting enabled by programming a 1 is used when
using the on-chip VCO with a passive loop filter or with an
active noninverting filter. It can also be set to 0, which is re-
quired if an active inverting loop filter is used.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1.
See the truth table in Table 7.
Counter Reset
DB4 is the counter reset bit for the ADF4360-7. When this is 1,
the R counter and the A, B counters are reset. For normal oper-
ation, this bit should be 0.
Core Power Level
PC1 and PC2 set the power level in the VCO core. The recom-
mended setting is 5 mA. See the truth table in Table 7.
ADF4360-7 Data Sheet
Rev. E | Page 20 of 28
N COUNTER LATCH
Table 8 shows the input data format for programming the
N counter latch.
A Counter Latch
A5 to A1 program the 5-bit A counter. The divide range is
0 (00000) to 31 (11111).
Reserved Bits
DB7 is a spare bit that is reserved. It should be programmed to 0.
B Counter Latch
B13 to B1 program the B counter. The divide range is 3
(00.....0011) to 8191 (11....111).
Overall Divide Range
The overall divide range is defined by ((P × B) + A), where P is
the prescaler value.
CP Gain
DB21 of the N counter latch in the ADF4360-7 is the charge
pump gain bit. When this is programmed to 1, Current Setting 2
is used. When programmed to 0, Current Setting 1 is used. This bit
can also be programmed through DB10 of the control latch. The bit
always reflects the latest value written to it, whether this is through
the control latch or the N counter latch.
Divide-by-2
DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2
function is chosen. When it is set to 0, normal operation occurs.
Divide-by-2 Select
DB23 is the divide-by-2 select bit. When programmed to 1, the
divide-by-2 output is selected as the prescaler input. When set
to 0, the fundamental is used as the prescaler input. For exam-
ple, using the output divide-by-2 feature and a PFD frequency
of 200 kHz, the user needs a value of N = 5,000 to generate
500 MHz. With the divide-by-2 select bit high, the user may
keep N = 2,500.
R COUNTER LATCH
With (C2, C1) = (0, 1), the R counter latch is programmed.
Table 9 shows the input data format for programming the
R counter latch.
R Counter
R1 to R14 set the counter divide ratio. The divide range is
1 (00......001) to 16383 (111......111).
Antibacklash Pulse Width
DB16 and DB17 set the antibacklash pulse width.
Lock Detect Precision
DB18 is the lock detect precision bit. This bit sets the number of
reference cycles with less than 15 ns phase error for entering the
locked state. With LDP at 1, five cycles are taken; with LDP at 0,
three cycles are taken.
Test Mode Bit
DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be pro-
grammed by the user.
Band Select Clock
These bits set a divider for the band select logic clock input. The
output of the R counter is by default the value used to clock the
band select logic, but if this value is too high (>1 MHz), a
divider can be switched on to divide the R counter output to a
smaller value (see Table 9).
Reserved Bits
DB23 to DB22 are spare bits that are reserved. They should be
programmed to 0.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

ADF4360-7BCPZRL

Mfr. #:
Buy ADF4360-7BCPZRL
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Intg Integer-N VCO Out Freq 350-1800
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet