NB3V110xC Series
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Table 5. RECOMMENDED OPERATING CONDITIONS
Over operating free−air temperature range (unless otherwise noted)
Symbol
Condition Min Typ Max Unit
V
DD
Supply voltage range
3.3 V supply 3.0 3.3 3.6
V
2.5 V supply 2.3 2.5 2.7
1.8 V supply 1.71 1.8 1.89
V
IL
Low−level input voltage
V
DD
= 3.0 V to 3.6 V V
DD
/2 –
600
mV
V
DD
= 2.3 V to 2.7 V V
DD
/2 –
400
V
DD
= 1.71 V to 1.89 V 0.3xV
DD
V
V
IH
High−level input voltage
V
DD
= 3.0 V to 3.6 V V
DD
/2 +
600
mV
V
DD
= 2.3 V to 2.7 V V
DD
/2 +
400
V
DD
= 1.71 V to 1.89 V 0.7xV
DD
V
V
th
Input threshold voltage
V
DD
= 2.3 V to 3.6 V V
DD
/2 V
V
DD
= 1.71 V to 1.89 V V
DD
/2 V
t
r
/ t
f
Input slew rate (Note 4) 1 4 V/ns
t
w
Minimum pulse width at CLKIN
V
DD
= 3.0 V to 3.6 V 1.8
ns
V
DD
= 2.3 V to 2.7 V 2.75
V
DD
= 1.71 V to 1.89 V 3.75
fCLK LVCMOS clock Input Frequency
V
DD
= 3.0 V to 3.6 V DC 250
MHz
V
DD
= 2.3 V to 2.7 V DC 180
V
DD
= 1.71 V to 1.89 V DC 133
T
A
Operating free−air temperature –40 105 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Guaranteed by Design.
NB3V110xC Series
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5
Table 6. DEVICE CHARACTERISTICS Over recommended operating free−air temperature range (unless otherwise noted) (Note 5)
Symbol
Parameter Condition Min Typ Max Unit
OVERALL PARAMETERS FOR ALL VERSIONS
I
DD
Static device current
OE = V
DD
; CLKIN = 0 V or V
DD
; I
O
= 0 mA; V
DD
=
3.6 V
0.2
mA
OE = V
DD
; CLKIN = 0 V or V
DD
; I
O
= 0 mA; V
DD
=
2.7 V
0.2
OE = V
DD
; CLKIN = 0 V or V
DD
; I
O
= 0 mA; V
DD
=
1.89 V
0.2
I
PD
Power down current
OE = 0 V; CLKIN = 0 V or V
DD
; I
O
= 0 mA; V
DD
=
3.6 V, 2.7 V or 1.89 V (For 1102C, 1103C, 1104C)
60
mA
OE = 0 V; CLKIN = 0 V or V
DD
; I
O
= 0 mA; V
DD
=
3.6 V, 2.7 V or 1.89 V (For 1106C, 1108C)
75
C
PD
Power dissipation capacitance per out-
put (Note 6)
V
DD
= 3.3 V; f = 10 MHz 9
pF
V
DD
= 2.5 V; f = 10 MHz 9
V
DD
= 1.8 V; f = 10 MHz 9
I
I
Input leakage current at OE
V
I
= 0 V or V
DD
, V
DD
= 3.6 V or 2.7 V
± 8
mA
Input leakage current at CLKIN ± 8
Input leakage current at OE, CLKIN V
I
= 0 V or V
DD
, V
DD
= 1.89 V ± 8
R
OUT
Output impedance
V
DD
= 3.3 V 40
W
V
DD
= 2.5 V 45
V
DD
= 1.8 V 60
f
OUT
Output frequency
V
DD
= 3.0 V to 3.6 V DC 250
MHz
V
DD
= 2.3 V to 2.7 V DC 180
V
DD
= 1.71 V to 1.89 V DC 133
OUTPUT PARAMETERS FOR V
DD
= 3.3 V + 0.3 V
V
OH
High−level output voltage
V
DD
= 3 V, I
OH
= –0.1 mA 2.9
V
V
DD
= 3 V, I
OH
= –8 mA 2.5
V
DD
= 3 V, I
OH
= –12 mA 2.2
V
OL
Low−level output voltage
V
DD
= 3 V, I
OL
= 0.1 mA 0.1
V
V
DD
= 3 V, I
OL
= 8 mA 0.5
V
DD
= 3 V, I
OL
= 12 mA 0.8
t
PLH
, t
PHL
Propagation delay (Note 7) CLKIN to Qn 0.8 2.0 ns
t
sk(o)
Output skew (Note 7)
Equal load of each output 85°C 50
ps
Equal load of each output 105°C 60
t
r
/t
f
Rise and fall time 20%–80% (V
OH
− V
OL
) 0.12 0.8 ns
t
DIS
Output disable time (Note 7) OE to Qn 6 ns
t
EN
Output enable time (Note 7) OE to Qn 6 ns
t
sk(p)
Pulse skew; tPLH(Qn) – tPHL(Qn) (Note 8) To be measured with input duty cycle of 50% 180 ps
t
sk(pp)
Part−to−part skew Under equal operating conditions for two parts 0.5 ns
T
jit(
f
)
Additive jitter rms
12 kHz...20 MHz f
OUT
= 100 MHz
100 fs
12 kHz...20 MHz f
OUT
= 156.25 MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All typical values are at respective nominal V
DD
. For switching characteristics, outputs are terminated to 50 W to V
DD
/2 (see Figure 2).
6. This is the formula for the power dissipation calculation.
Ptot = Pstat + Pdyn + PCload [W] P
stat
= V
DD
x I
DD
[W]
P
dyn
= C
PD
x V
DD
2 x ƒ x n [W]
P
Cload
= C
load
x V
DD
2 x ƒ x n [W]
n = Number of switching output pins
7. With rail to rail input clock.
8. t
sk(p)
depends on output rise− and fall−time (t
r
/t
f
). The output duty−cycle can be calculated: odc = (t
w(OUT)
± t
sk(p)
)/t
period
; t
w(OUT)
is
pulse−width of ideal output waveform and tperiod is 1/f
OUT
.
NB3V110xC Series
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6
Table 7. DEVICE CHARACTERISTICS (continued)
Over recommended operating free−air temperature range (unless otherwise noted) (Note 5)
Symbol
Parameter Condition Min Typ Max Unit
OUTPUT PARAMETERS FOR V
DD
= 2.5 V + 0.2 V
V
OH
High−level output voltage
V
DD
= 2.3 V, I
OH
= –0.1 mA 2.2
V
V
DD
= 2.3 V, I
OH
= –8 mA 1.7
V
OL
Low−level output voltage
V
DD
= 2.3 V, I
OL
= 0.1 mA 0.1
V
V
DD
= 2.3 V, I
OL
= 8 mA 0.5
t
PLH
, t
PHL
Propagation delay (Note 10) CLKIN to Qn 1.8 ns
t
sk(o)
Output skew (Note 10)
Equal load of each output 85°C 50
ps
Equal load of each output 105°C 60
t
r
/t
f
Rise and fall time 20%–80% (V
OH
− V
OL
) 0.12 1.2 ns
t
DIS
Output disable time (Note 10) OE to Qn 10 ns
t
EN
Output enable time (Note 10) OE to Qn 10 ns
t
sk(p)
Pulse skew ;
t
PLH(Qn) – tPHL(Qn)
(Note 9)
To be measured with input duty cycle of 50% 220 ps
t
sk(pp)
Part−to−part skew Under equal operating conditions for two
parts
1.2 ns
tjit
(
f
)
Additive jitter rms
12 kHz...20 MHz f
OUT
= 100 MHz 150
fs
12 kHz...20 MHz f
OUT
= 156.25 MHz 100
OUTPUT PARAMETERS FOR V
DD
= 1.8 V + 5%
V
OH
High−level output voltage
V
DD
= 1.71 V, I
OH
= –0.1 mA 1.6
V
V
DD
= 1.71 V, I
OH
= –4 mA 0.75xV
DD
V
OL
Low−level output voltage
V
DD
= 1.71 V, I
OL
= 0.1 mA 0.1
V
V
DD
= 1.71 V, I
OL
= 4 mA 0.25xV
DD
t
PLH
, t
PHL
Propagation delay (Note 10) CLKIN to Qn 1.8 3.5 ns
t
sk(o)
Output skew (Note 10) Equal load of each output 75 ps
t
r
/t
f
Rise and fall time 20%–80% (V
OH
− V
OL
) 0.17 1.2 ns
t
DIS
Output disable time (Note 10) OE to Qn 10 ns
t
EN
Output enable time (Note 10) OE to Qn 10 ns
t
sk(p)
Pulse skew ;
t
PLH(Qn) – tPHL(Qn)
(Note 9)
To be measured with input duty cycle of 50% 450 ps
t
sk(pp)
Part−to−part skew Under equal operating conditions for two
parts
1.2 ns
tjit
(
f
)
Additive jitter rms 12 kHz...20 MHz, f
OUT
= 100 MHz 200 fs
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. t
sk(p)
depends on output rise− and fall−time (t
r
/t
f
). The output duty−cycle can be calculated: odc = (t
w(OUT)
± t
sk(p)
)/t
period
; t
w(OUT)
is
pulse−width of ideal output waveform and tperiod is 1/f
OUT
.
10.With rail to rail input clock.

NB3V1102CDTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer FANOUT BUFFER WITH 2
Lifecycle:
New from this manufacturer.
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