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ACPL-W343-060E

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
16
Rail-to-Rail Output
Figure 29 shows a typical gate driver’s high current output
stage with 3 bipolar transistors in darlington con guration.
During the output high transition, the output voltage rises
rapidly to within 3 diode drops of V
CC
. To ensure the V
OUT
is at V
CC
in order to achieve IGBT rated V
CE(ON)
voltage. The
level of V
CC
will be need to be raised to beyond V
CC
+3(V
BE
)
to account for the diode drops. And to limit the output
voltage to V
CC
, a pull-down resistor, R
PULL-DOWN
between
the output and V
EE
is recommended to sink a static current
while the output is high.
Figure 29. Typical gate driver with output stage in darlington con guration
Figure 30. ACPL-P343/W343 with PMOS and NMOS output stage for rail-to-rail output voltage
1
2
3
4
8
7
6
5
V
CC
V
OUT
V
EE
CATHODE
NC
ANODE
NC
R
G
R
PULL-DOWN
ACPL-P343 uses a power PMOS to deliver the large current
and pull it to V
CC
to achieve rail-to-rail output voltage
as shown in Figure 30. This ensures that the IGBT’s gate
voltage is driven to the optimum intended level with no
power loss across IGBT even when an unstable power
supply is used.
V
CC
V
EE
1
2
3
6
5
4
CATHODE
NC
ANODE
V
OUT
17
Selecting the Gate Resistor (Rg)
Step 1: Calculate Rg minimum from the I
OL
peak speci cation. The IGBT and Rg in Figure 28 can be analyzed as a simple
RC circuit with a voltage supplied by ACPL-P343/W343.
Rg ≥
V
CC
– V
EE
– V
OL
I
OLPEAK
=
15 V + 5 V – 2.9 V
4A
= 4.3 5
The V
OL
value of 2.9 V in the previous equation is the V
OL
at the peak current of 4.0 A (see Figure 7).
Step 1: Check the ACPL-P343/W343 power dissipation and increase Rg if necessary. The ACPL-P343/W343 total power
dissipation (P
T
) is equal to the sum of the emitter power (P
E
) and the output power (P
O
).
P
T
= P
E
+ P
O
P
E
= I
F
• V
F
• Duty Cycle
P
O
= P
O(BIAS)
+ P
O(SWITCHING)
= I
CC
• (V
CC
-V
EE
) + E
SW
(Rg;Cg) • f
Using I
F
(worst case) = 16 mA, Rg = 5 , Max Duty Cycle = 80%, Cg = 25 nF, f = 25 kHz and T
A
max = 85° C:
P
E
= 16 mA • 1.95 V • 0.8 = 25 mW
P
O
= 3 mA • 20 V + 5 J • 25 kHz
= 60 mW + 125 mW
= 185 mW < 700 mW (P
O(MAX)
@ 85° C)
The value of 3 mA for I
CC
in the previous equation is the maximum I
CC
over the entire operating temperature range.
Since P
O
is less than P
O(MAX)
, Rg = 5 is alright for the power dissipation.
Figure 31. Energy Dissipated in the ACPL-P343/W343 for each IGBT switching
cycle
2.0E-05
2.5E-05
3.0E-05
1.0E-05
1.5E-05
0.0E+00
5.0E-06
E
SW
- ENERGY PER SWITCHING CYCLE - J
0 2468 10
Rg - Gate Resistance - 7
V
CC
= 30 V
V
CC
= 20 V
V
CC
= 15 V
18
LED Drive Circuit Considerations for High CMR Performance
Figure 32 shows the recommended drive circuit for the
ACPL-P343/W343 that gives optimum common-mode
rejection. The two current setting resistors balance the
common mode impedances at the LED’s anode and
cathode. Common-mode transients can be capacitive
coupled from the LED anode, through C
LA
(or cathode
through C
LC
) to the output-side ground causing current
to be shunted away from the LED (which is not wanted
when the LED should be on) or conversely cause current
to be injected into the LED (which is not wanted when the
LED should be o ).
Table 8 shows the directions of I
LP
and I
LN
depend on the
polarity of the common-mode transient. For transients
occurring when the LED is on, common-mode rejection
(CM
H
, since the output is at “high” state) depends on
LED current (I
F
). For conditions where I
F
is close to the
switching threshold (I
FLH
), CM
H
also depends on the
extent to which I
LP
and I
LN
balance each other. In other
words, any condition where a common-mode transient
causes a momentary decrease in I
F
(i.e. when dV
CM
/dt > 0
and |I
LP
| > |I
LN
|, referring to Table 8) will cause a common-
mode failure for transients which are fast enough.
Likewise for a common-mode transient that occurs when
the LED is o (i.e. CM
L
, since the output is at “low” state),
if an imbalance between I
LP
and I
LN
results in a transient
I
F
equal to or greater than the switching threshold of the
optocoupler, the transient “signal” may cause the output
to spike above 1 V, which constitutes a CM
L
failure. The
balanced I
LED
-setting resistors help equalize the common
mode voltage change at the anode and cathode. The
shunt drive input circuit will also help to achieve high CM
L
performance by shunting the LED in the o state.
+5 V
R
1
R
2
V
CC
V
EE
1
2
3
6
5
4
CATHODE
ANODE
V
OUT
I
LP
I
LN
C
LA
C
LC
V
DD
= 5.0 V:
R
1
= 205 7 ±1%
R
2
= 137 7 ±1%
R
1
/R
2
≈ 1.5
Figure 32. Recommended high-CMR drive circuit for the ACPL-P343/W343
Table 8. Common Mode Pulse Polarity and LED current Transients
dV
CM
/dt I
LP
Direction I
LP
Direction
If |I
LP
| < |I
LN
|,
I
F
is momentarily
If |I
LP
| > |I
LN
|,
I
F
is momentarily
Positive (>0) Away from LED anode
through C
LA
Away from LED cathode
through C
LC
Increase Decrease
Negative(<0) Toward LED anode
through C
LA
Toward LED cathode
through C
LC
Decrease Increase
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ACPL-W343-060E

Mfr. #:
Buy ACPL-W343-060E
Manufacturer:
Broadcom / Avago
Description:
Logic Output Optocouplers Gate Drive Opto
Lifecycle:
New from this manufacturer.
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