19
Dead Time and Propagation Delay Speci cations
The ACPL-P343/W343 includes a Propagation Delay Dif-
ference (PDD) speci cation intended to help designers
minimize dead time” in their power inverter designs. Dead
time is the time period during which both the high and
low side power transistors (Q1 and Q2 in Figure 28) are o .
Any overlap in Q1 and Q2 conduction will result in large
currents  owing through the power devices between the
high and low voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn o of LED1)
so that under worst-case conditions, transistor Q1 has
just turned o when transistor Q2 turns on, as shown in
Figure 33. The amount of delay necessary to achieve this
condition is equal to the maximum value of the propa-
gation delay di erence speci cation, PDD
MAX
, which is
speci ed to be 100 ns over the operating temperature
range of 40° C to 105° C.
Delaying the LED signal by the maximum propagation
delay di erence ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the di erence between the maximum and minimum
propagation delay di erence speci cations as shown in
Figure 34. The maximum dead time for the ACPL-P343/
W343 is 200 ns (= 100 ns – (-100 ns)) over an operating
temperature range of -40° C to 105° C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical IGBTs.
Figure 33. Minimum LED skew for zero dead time Figure 34. Waveforms for dead time
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Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-2928EN - November 14, 2011
LED Current Input with Hysteresis
The detector has optical receiver input stage with built in
Schmitt trigger to provide logic compatible waveforms,
eliminating the need for additional wave shaping. The
hysteresis (Figure 12) provides di erential mode noise
immunity and minimizes the potential for output signal
chatter.
Under Voltage Lockout
The ACPL-P343/W343 Under Voltage Lockout (UVLO)
feature is designed to prevent the application of insu -
cient gate voltage to the IGBT by forcing the ACPL-P343/
W343 output low during power-up. IGBTs typically require
gate voltages of 15 V to achieve their rated V
CE(ON)
voltage.
At gate voltages below 13 V typically, the V
CE(ON)
voltage
increases dramatically, especially at higher currents. At
very low gate voltages (below 10 V), the IGBT may operate
in the linear region and quickly overheat. The UVLO
function causes the output to be clamped whenever
insu cient operating supply (V
CC
) is applied. Once V
CC
exceeds V
UVLO+
(the positive-going UVLO threshold), the
UVLO clamp is released to allow the device output to turn
on in response to input signals.
Thermal Model for ACPL-P343/W343 Stretched SO6
Package Optocoupler
De nitions:
R
11
: Junction to Ambient Thermal Resistance of LED due
to heating of LED
R
12
: Junction to Ambient Thermal Resistance of LED due
to heating of Detector (Output IC)
R
21
: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of LED.
R
22
: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of Detector (Output IC).
P
1
: Power dissipation of LED (W).
P
2
: Power dissipation of Detector / Output IC (W).
T
1
: Junction temperature of LED (°C).
T
2
: Junction temperature of Detector (°C).
Ta: Ambient temperature.
Ambient Temperature: Junction to Ambient Thermal Re-
sistances were measured approximately 1.25 cm above
optocoupler at ~23° C in still air
Thermal Resistance °C/W
R
11
135
R
12
27
R
21
39
R
22
47
This thermal model assumes that an 6-pin single-channel
plastic package optocoupler is soldered into a 7.62 cm x
7.62 cm printed circuit board (PCB) per JEDEC standards.
The temperature at the LED and Detector junctions of
the optocoupler can be calculated using the equations
below.
T
1
= (R
11
* P
1
+ R
12
* P
2
) + Ta (1)
T
2
= (R
21
* P
1
+ R
22
* P
2
) + Ta (2)
Using the given thermal resistances and thermal model
formula in this datasheet, we can calculate the junction
temperature for both LED and the output detector. Both
junction temperature should be within the absolute
maximum rating.
For example, given P
1
= 25 mW, P
2
= 185 mW, Ta = 85° C:
LED junction temperature,
T
1
= (R
11
* P
1
+ R
12
* P
2
) + Ta
= (135 * 0.025 + 27 * 0.185) + 85
= 93.4° C
Output IC junction temperature,
T
2
= (R
21
* P
1
+ R
22
* P
2
) + Ta
= (39 *0.025 + 47 * 0.185) + 85
= 94.7° C
T
1
and T
2
should be limited to 125° C based on the board
layout and part placement.
Related Application Noted
AN5336 – Gate Drive Optocoupler Basic Design for IGBT/
MOSFET
AN1043 – Common-Mode Noise: Sources and Solutions
AV02-0310EN – Plastics Optocouplers Product ESD and
Moisture Sensitivity

ACPL-W343-060E

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Logic Output Optocouplers Gate Drive Opto
Lifecycle:
New from this manufacturer.
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