8
Notes:
1. Derate linearly above 70° C free-air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 s. This value is intended to allow for component tolerances for designs with I
O
peak minimum = 3.0 A. See applications
section for additional details on limiting I
OH
peak.
3. Derate linearly above 85° C free-air temperature at a rate of 16.9 mW/°C .
4. Derate linearly above 85° C free-air temperature at a rate of 15.3 mW/°C . The maximum LED junction temperature should not exceed 125° C.
5. Maximum pulse width = 50 s.
6. Output is sourced at -3.0 A with a maximum pulse width = 10 s. V
CC
-V
O
is measured to ensure 15 V or below.
7. Output is sourced at 3.0 A with a maximum pulse width = 10 s. V
O
-V
EE
is measured to ensure 15 V or below.
8. Output is sourced at -3.0 A/3.0 A with a maximum pulse width = 10 s.
9. In this test V
OH
is measured with a DC load current. When driving capacitive loads, V
OH
will approach V
CC
as I
OH
approaches zero amps.
10. Maximum pulse width = 1 ms.
11. Pulse Width Distortion (PWD) is de ned as |t
PHL
-t
PLH
| for any given device.
12. The di erence between t
PHL
and t
PLH
between any two ACPL-P343 parts under the same test condition.
13. Pin 2 needs to be connected to LED common.
14. Common mode transient immunity in the high state is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to assure that the
output will remain in the high state (i.e., V
O
> 15.0 V).
15. Common mode transient immunity in a low state is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to assure that the output
will remain in a low state (i.e., V
O
< 1.0 V).
16. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≤ 4500 V
RMS
for 1 second (leakage detection
current limit, I
I-O
< 5 A).
17. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≤ 6000 V
RMS
for 1 second (leakage detection
current limit, I
I-O
< 5 A).
18. Device considered a two-terminal device: pins 1, 2, and 3 shorted together and pins 4, 5 and 6 shorted together.
19. The device was mounted on a high conductivity test board as per JEDEC 51-7
