LTC1418
18
1418fa
For more information www.linear.com/LTC1418
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as
wide as possible.
Example Layout
Figures 12a, 12b, 12c and 12d show the schematic and
layout of a suggested evaluation board. The layout dem-
onstrates the proper use of decoupling capacitors and
ground plane with a 2-layer printed circuit board.
DIGITAL INTERFACE
The LTC1418 can operate in serial or parallel mode. In
parallel mode the ADC is designed to interface with mi-
croprocessors as a memory mapped device. The CS and
RD control inputs are common to all peripheral memory
interfacing. In serial mode only four digital interface lines
are required, SCLK, CONVST, EXTCLKIN and D
OUT
. SCLK,
the serial data shift clock can be an external input or sup-
plied by the LTC1418 internal clock.
Internal Clock
The ADC has an internal clock. In parallel output mode, the
internal clock is always used as the conversion clock. In
APPLICATIONS INFORMATION
Figure 12d. Suggested Evaluation Circuit Board—Solder Side Layout
1418 F12d
serial output mode either the internal clock or an external
clock may be used as the conversion clock (see Figure20).
The internal clock is factory trimmed to achieve a typical
conversion time of 3.4µs and a maximum conversion
time over the full operating temperature range of 4µs. No
external adjustments are required, and with the guaranteed
maximum acquisition time of 1µs, throughput performance
of 200ksps is assured.
Power Shutdown
The LTC1418 provides two power shutdown modes, nap
and sleep, to save power during inactive periods. The nap
mode reduces the power by 80% and leaves only the digital
logic and reference powered up. The wake-up time from
nap to active is 500ns (see Figure 13a). In sleep mode
all bias currents are shut down and only leakage current
remains—about 2µA. Wake-up time from sleep mode is
much slower since the reference circuit must power up
and settle to 0.005% for full 14-bit accuracy. Sleep mode
wake-up time is dependent on the value of the capacitor
connected to the REFCOMP (Pin 4). The wake-up time is
30ms with the recommended 10µF capacitor. Shutdown
is controlled by Pin 22 (SHDN); the ADC is in shutdown
when it is low. The shutdown mode is selected with Pin 25
(CS); low selects nap (see Figure 13b), high selects sleep.
