LTC1418
22
1418fa
For more information www.linear.com/LTC1418
APPLICATIONS INFORMATION
Figure 20. Functional Block Diagram for Serial Mode (SER/PAR = High)
THREE
STATE
BUFFER
THREE
STATE
BUFFER
23
RD
17
• • •
SCLK*
CS
25
EXTCLKIN*
16
EXT/INT*
BUSY
*PINS 16 TO 20 ARE LABELED WITH THEIR SERIAL FUNCTIONS
1418 F20
20
D
OUT
*
19
CLKOUT*
18
26
SHIFT
REGISTER
INTERNAL
CLOCK
16 CONVERSION CLOCK CYCLES
EOC
DATA
IN
14
DATA
OUT
CLOCK
INPUT
• • •
SAR
The SCLK is used to clock the shift register. Data may be
clocked out with the internal conversion clock operating as
a master by connecting CLKOUT (Pin 18) to SCLK (Pin17)
or with an external data clock applied to D3 (SCLK). The
minimum number of SCLK cycles required to transfer a
data word is 14. Normally, SCLK contains 16 clock cycles
for a word length of 16 bits; 14 bits with MSB first, fol-
lowed by two trailing zeros.
A logic high on RD disables SCLK and three-states D
OUT
. In
case of using a continuous SCLK, RD can be controlled to
limit the number of shift clocks to the desired number (i.e.,
16 cycles) and to three-state D
OUT
after the data transfer.
A logic high on CS three-states the D
OUT
output buffer.
It also inhibits conversion when it is tied high. In power
shutdown mode (SHDN = low), a high CS selects sleep
mode while a low CS selects nap mode. For normal serial
port operation, CS can be grounded.
D
OUT
outputs the serial data; 14 bits, MSB first, on the
falling edge of each SCLK (see Figures 21 and 22). If
16SCLKs are provided, the 14 data bits will be followed
by two zeros. The MSB (D13) will be valid on the first
rising and the first falling edge of the SCLK. D12 will be
valid on the second rising and the second falling edge as
will all the remaining bits
. The data may be captured on
either edge. The largest hold time margin is achieved if
data is captured on the rising edge of SCLK.
BUSY gives the end of conversion indication. When the
LTC1418 is configured as a master serial device, BUSY
can be used as a framing pulse and to three-state the se-
rial port after transferring the serial output data by tying
it to the RD pin.
Figures 22 to 25 show several serial modes of operation,
demonstrating the flexibility of the LTC1418 serial port.
SERIAL DATA OUTPUT DURING A CONVERSION
Using Internal Conversion Clock for Conversion and
Data Transfer
Figure 22 shows data from the previous conversion be-
ing clocked out during the conversion with the LTC1418
internal clock providing both the conversion clock and the
SCLK. The internal clock has been optimized for the fast-
est conversion time, consequently this mode can provide
the best overall speed performance. To select an internal
conversion clock, tie EXT/INT (Pin 20) low. The internal
