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LTC1418AIG#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
LTC1418
7
1418fa
For more information www.linear.com/LTC1418
TYPICAL PERFORMANCE CHARACTERISTICS
V
DD
Supply Current vs
Temperature (Unipolar Mode)
V
DD
Supply Current vs
Temperature (Bipolar Mode)
V
SS
Supply Current vs
Temperature (Bipolar Mode)
V
DD
Supply Current vs Sampling
Frequency (Unipolar Mode)
V
DD
Supply Current vs Sampling
Frequency (Bipolar Mode)
V
SS
Supply Current vs Sampling
Frequency (Bipolar Mode)
Power Supply Feedthrough
vs Ripple Frequency
Input Common Mode Rejection
vs Input Frequency
Input Offset Voltage Shift
vs Source Resistance
FREQUENCY (Hz)
1k
DISTORTION (dB)
10k 100k
1418 G10
1M 10M
0
–20
–40
–60
–80
–100
–120
V
SS
V
DD
DGND
INPUT FREQUENCY (Hz)
1 10
COMMON MODE REJECTION (dB)
10k 100k
90
80
70
60
50
40
30
20
10
0
1418 G11
100 1k 1M
INPUT SOURCE RESISTANCE (Ω)
CHANGE IN OFFSET VOLTAGE (LSB)
10
9
8
7
6
5
4
3
2
1
0
10 1k 10k 1M
1418 G12
100 100k
TEMPERATURE (°C)
–75
V
DD
SUPPLY CURRENT (mA)
75
5
4
3
2
1
0
1418 G13
–50 150
–25
0 25 50 100
125
TEMPERATURE (°C)
–75
V
DD
SUPPLY CURRENT (mA)
75
1418 G14
–50 150
–25
0 25 50 100
125
5
4
3
2
1
0
TEMPERATURE (°C)
–75
V
SS
SUPPLY CURRENT (mA)
75
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1418 G13
–50 150
–25
0 25 50 100
125
SAMPLING FREQUENCY (kHz)
0
V
DD
SUPPLY CURRENT (mA)
50
100 150 200
1418 G16
250 300
5
4
3
2
1
0
SAMPLING FREQUENCY (kHz)
0
V
DD
SUPPLY CURRENT (mA)
50
100
150 200
1418 G17
250 300
5
4
3
2
1
0
SAMPLING FREQUENCY (kHz)
0
V
SS
SUPPLY CURRENT (mA)
50
100
150 200
1418 G18
250 300
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
LTC1418
8
1418fa
For more information www.linear.com/LTC1418
PIN FUNCTIONS
A
IN
+
(Pin 1): Positive Analog Input.
A
IN
–
(Pin 2): Negative Analog Input.
V
REF
(Pin 3): 2.50V Reference Output. Bypass to AGND
with 1µF.
REFCOMP (Pin 4): 4.096V Reference Bypass Pin. Bypass
to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs (Paral-
lel). D13 is the most significant bit.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 (Pin 15): Three-State Data Output (Parallel).
D4 (EXTCLKIN) (Pin 16): Three-State Data Output (Par-
allel). Conversion clock input (serial) when Pin 20 (EXT/
INT) is tied high.
D3 (SCLK) (
Pin 17): Three-State Data Output (Parallel).
Data clock input (serial).
D2 (CLKOUT) (Pin 18): Three-State Data Output (Parallel).
Conversion clock output (serial).
D1 (D
OUT
) (Pin 19): Three-State Data Output (Parallel).
Serial data output (serial).
D0 (EXT/INT) (Pin 20): Three-State Data Output (Parallel).
Conversion clock selector (serial). An input low enables
the internal conversion clock. An input high indicates
an external conversion clock will be assigned to Pin 16
(EXTCLKIN).
SER/PAR (Pin 21): Data Output Mode.
SHDN (Pin 22): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
RD (Pin 23): Read Input. This enables the output drivers
when CS is low.
CONVST (Pin 24):
Conversion Start Signal. This active low
signal starts a conversion on its falling edge.
CS (Pin 25): Chip Select. This input must be low for the
ADC to recognize the CONVST and RD inputs. CS also
sets the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
BUSY (Pin 26): The BUSY Output Shows the Converter
Status. It is low when a conversion is in progress.
V
SS
(Pin 27): Negative Supply, –5V for Bipolar Operation.
Bypass to AGND with 10µF tantalum in parallel with 0.1µF
ceramic. Analog ground for unipolar operation.
V
DD
(Pin 28): 5V Positive Supply. Bypass to AGND with
10µF tantalum in parallel with 0.1µF ceramic.
TEST CIRCUITS
1k C
L
DBN
DGND
A) HI-Z TO V
OH
AND V
OL
TO V
OH
C
L
DBN
1k
5V
B) HI-Z TO V
OL
AND V
OH
TO V
OL
DGND
1418 TC01
1k
30pF
DBN
A) V
OH
TO HI-Z
30pF
DBN
1k
5V
B) V
OL
TO HI-Z
1418 TC02
Load Circuits for Access Timing
Load Circuits for Output Float Delay
LTC1418
9
1418fa
For more information www.linear.com/LTC1418
BLOCK DIAGRAM
CONVERSION DETAILS
The LTC1418 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an ana-
log signal to a 14-bit parallel or serial output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs (please refer to Digital Interface section
for the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive ap-
proximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
14-BIT CAPACITIVE DAC
COMPREF AMP
2.5V REF
8k
REFCOMP
4.096V
2.5V
C
SAMPLE
C
SAMPLE
•
•
•
D13
D0
BUSY
CONTROL LOGIC
D2/(CLKOUT)
INTERNAL
CLOCK
SHDND0 (EXT/INT)D4 (EXTCLKIN) CONVST RD CS
ZEROING SWITCHES
D1/(D
OUT
)
NOTE: PIN NAMES IN PARENTHESES
REFER TO SERIAL MODE
D3/(SCLK)
V
DD
: 5V
V
SS
: 0V FOR UNIPOLAR MODE
–5V FOR BIPOLAR MODE
A
IN
+
A
IN
–
V
REF
AGND
DGND
14
1418 BD
+
–
SUCCESSIVE APPROXIMATION
REGISTER
SHIFT
REGISTER
SER/PAR
MUX
APPLICATIONS INFORMATION
Figure 1. Simplified Block Diagram
OUTPUT
LATCH
SAR
C
DAC
+
C
DAC
–
V
DAC
–
V
DAC
+
–
+
COMP
D13
D0
14
HOLD
HOLD
HOLD
A
IN
+
A
IN
–
ZEROING SWITCHES
C
SAMPLE
–
C
SAMPLE
+
HOLD
SAMPLE
SAMPLE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

LTC1418AIG#PBF

Mfr. #:
Buy LTC1418AIG#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC L Pwr, 14-B, 200ksps ADC w/ Serial & Par
Lifecycle:
New from this manufacturer.
Delivery:
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