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NBSG86ABAEVB

P1-P3P4-P6P7-P9P10-P12P13-P14
Semiconductor Components Industries, LLC, 2004
May, 2004 − Rev. 8
1 Publication Order Number:
NBSG86A/D
NBSG86A
2.5V/3.3VSiGe Differential
Smart Gate with Output
Level Select
The NBSG86A is a multi−function differential Logic Gate which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaComm family of high
performance Silicon Germanium products. The device is housed in a
low profile 4x4 mm, 16−pin, flip−chip BGA or a 3x3 mm 16 pin QFN
package.
Differential inputs incorporate internal 50 termination resistors
and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to
program the peak−to−peak output amplitude between 0 and 800 mV
in five discrete steps.
The NBSG86A employs input default circuitry so that under open
input conditions (D
x
, D
x
, VTD
x
, VTD
x,
VTSEL) the outputs of the
device will remain stable.
• Maximum Input Clock Frequency > 8 GHz Typical
• Maximum Input Data Rate > 8 Gb/s Typical
• 165 ps Typical Propagation Delay
• 40 ps Typical Rise and Fall Times
• Selectable Swing PECL Output with Operating Range:
V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
• Selectable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
• Selectable Output Level (0 V, 200 mV, 400 mV,
600 mV, or 800 mV Peak−to−Peak Output)
• 50 Internal Input Termination Resistors
*For further details, refer to Application Note
AND8002/D
FCBGA−16
BA SUFFIX
CASE 489
MARKING
DIAGRAM*
SG
86A
Device Package Shipping
†
ORDERING INFORMATION
NBSG86ABA 4x4 mm
FCBGA−16
100 Units/Tray
NBSG86ABAR2 4x4 mm
FCBGA−16
500/
Tape & Reel
LYW
Board Description
NBSG86ABAEVB NBSG86ABA Evaluation Board
http://onsemi.com
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
SG86A
ALYW
QFN−16
MN SUFFIX
CASE 485G
NBSG86AMN 3x3 mm
QFN−16
123 Units/Rail
NBSG86AMNR2 3x3 mm
QFN−16
3000/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
NBSG86A
http://onsemi.com
2
VTD1
SEL
SEL
OLS
VTD0 D0
VTSEL
D1 D1 VTD1
V
CC
V
EE
D0 VTD0
Q
Q
A
B
C
D
1234
Figure 1. BGA−16 Pinout (Top View)
VTD1 D1 D1 VTD1
VTD0 D0 D0 VTD0
V
EE
Q
Q
V
CC
OLS
SEL
SEL
VTSEL
5678
16 15 14 13
12
11
10
9
1
2
3
4
NBSG86A
Exposed Pad
(EP)
Figure 2. QFN−16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA QFN
Name I/O Description
C2 1 OLS
(Note 3)
Input Input Pin for the Output Level Select (OLS). See Table 2.
C1 2 SEL ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Select Logic Input.
B1 3 SEL ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Select Logic Input.
B2 4 VTSEL − Common Internal 50 Termination Pin for SEL/SEL. See Table 7. (Note 1)
A1 5 VTD1 − Internal 50 termination pin. See Table 7. (Note 1)
A2 6 D1 ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input 1. Internal 75 k to V
EE
.
A3 7 D1 ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input 1. Internal 75 k to V
EE
and 36.5 k to V
CC
.
A4 8 VTD1 − Internal 50 Termination Pin. See Table 7. (Note 1)
B3 9 V
CC
− Positive Supply Voltage (Note 2)
B4 10 Q RSECL Output Noninverted Differential Output. Typically Terminated with 50 Resistor to
V
TT
= V
CC
− 2 V.
C4 11 Q RSECL Output Inverted Differential Output. Typically Terminated with 50 Resistor to
V
TT
= V
CC
− 2 V
C3 12 V
EE
− Negative Supply Voltage (Note 2)
D4 13 VTD0 − Internal 50 Termination Pin. See Table 7. (Note 1)
D3 14 D0 ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input 0. Internal 75 k to V
EE
and 36.5 k to V
CC
.
D2 15 D0 ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input 0. Internal 75 k to V
EE
.
D1 16 VTD0 − Internal 50 Termination Pin. See Table 7. (Note 1)
N/A − EP − Exposed Pad. The thermally exposed pad on package bottom (see case drawing)
must be attached to a heat−sinking conduit.
1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage,
and if no signal is applied then the device will be susceptible to self−oscillation.
2. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation.
3. When an output level of 400 mV is desired and V
CC
− V
EE
> 3.0 V, 2 k resistor should be connected from OLS pin to V
EE
.
NBSG86A
http://onsemi.com
3
Table 2. OUTPUT LEVEL SELECT OLS
OLS Q/Q VPP OLS Sensitivity
V
CC
800 mV OLS − 75 mV
V
CC
− 0.4 V 200 mV OLS 150 mV
V
CC
− 0.8 V 600 mV OLS 100 mV
V
CC
− 1.2 V 0 OLS 75 mV
V
EE
(Note 4) 400 mV OLS 100 mV
Float 600 mV N/A
4. When an output level of 400 mV is desired and V
CC
− V
EE
> 3.0 V, 2.0 k resistor should be
connected from OLS to V
EE
.
Figure 3. Logic Diagram
D0
Q
SEL
VTD0
Q
SEL
VTD0
50
50
D0
D1
VTD1
VTD1
50
50
D1
50
50
VTSEL
R
1
R
2
R
1
R
1
R
2
R
1
Q
SEL
VTD0
Q
SEL
VTD0
50
50
VTD1
VTD1
50
50
50
50
VTSEL
Figure 4. Configuration for AND/NAND Function
V
CC
VT or
V
BB
D0
D0
D1
D1
V
EE
V
CC
Table 3. AND/NAND TRUTH TABLE (Note 5)
*
D0 D1 SEL Q
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
5. D0, D1, SEL are inverse of D0, D1, SEL unless specified other-
wise.
P1-P3P4-P6P7-P9P10-P12P13-P14

NBSG86ABAEVB

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Buy NBSG86ABAEVB
Manufacturer:
ON Semiconductor
Description:
Clock & Timer Development Tools BBG NBSG86ABA EVAL BOARD
Lifecycle:
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