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NBSG86ABAEVB

P1-P3P4-P6P7-P9P10-P12P13-P14
NBSG86A
http://onsemi.com
7
Table 11. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT V
CC
= 3.3 V; V
EE
= 0 V (Note 15)
−40°C 25°C 70°C(BGA)/85°C(QFN)***
Symbol Characteristic
Min Typ Max Min Typ Max Min Typ Max
Unit
I
EE
Negative Power Supply Current 23 30 39 23 30 39 23 30 39 mA
V
OH
Output HIGH Voltage (Note 16) 2260 2310 2360 2290 2340 2390 2315 2365 2415 mV
V
OL
Output LOW Voltage (Note 16)
(OLS = V
CC
)
(OLS = V
CC
− 0.4 V)
(OLS = V
CC
− 0.8 V, OLS = FLOAT)
(OLS = V
CC
− 1.2 V)
**(OLS = V
EE
)
1320
2030
1550
2260
1785
1470
2090
1670
2310
1875
1620
2150
1790
2360
1965
1360
2065
1585
2290
1820
1510
2125
1705
2340
1910
1660
2185
1825
2390
2000
1390
2090
1615
2315
1850
1540
2150
1735
2365
1940
1690
2210
1855
2415
2030
mV
V
OUTPP
Output Voltage Amplitude
(OLS = V
CC
)
(OLS = V
CC
− 0.4 V)
(OLS = V
CC
− 0.8 V, OLS = FLOAT)
(OLS = V
CC
− 1.2 V)
**(OLS = V
EE
)
750
130
550
0
345
840
220
640
0
435
740
125
545
0
340
830
215
635
0
430
735
125
540
0
335
825
215
630
0
425
mV
V
IH
Input HIGH Voltage (Single−Ended)
(Note 18) D, D
V
EE
+
1275
V
CC
−
1000*
V
CC
V
EE
+
1275
V
CC
−
1000*
V
CC
V
EE
+
1275
V
CC
−
1000*
V
CC
mV
V
IL
Input LOW Voltage (Single−Ended)
(Note 19) D, D
V
IH
−
2600
V
CC
−
1400*
V
IH
−
150
V
IH
−
2600
V
CC
−
1400*
V
IH
−
150
V
IH
−
2600
V
CC
−
1400*
V
IH
−
150
mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 17)
1.2 3.3 1.2 3.3 1.2 3.3 V
R
TIN
Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55
I
IH
Input HIGH Current (@V
IH
) D, D
SEL
30
5
100
50
30
5
100
50
30
5
100
50
A
I
IL
Input LOW Current (@V
IL
) D, D
SEL
20
5
100
50
20
5
100
50
20
5
100
50
A
NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15.Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925 V to −0.165 V.
16.All loading with 50 to V
CC
− 2.0 V.
17.V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
18.V
IH
cannot exceed V
CC
.
19.V
IL
always V
EE
.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and V
CC
− V
EE
> 3.0 V, a 2 k resistor should be connected from OLS to V
EE
.
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have
maximum ambient temperature specification of 85°C.
NBSG86A
http://onsemi.com
8
Table 12. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT V
CC
= 0 V; V
EE
= −3.465 V to −2.375 V (Note 20)
−40°C 25°C 70°C(BGA)/85°C(QFN)***
Symbol Characteristic
Min Typ Max Min Typ Max Min Typ Max
Unit
I
EE
Negative Power Supply Current 23 30 39 23 30 39 23 30 39 mA
V
OH
Output HIGH Voltage (Note 21) −1040 −990 −940 −1010 −960 −910 −985 −935 −885 mV
V
OL
Output LOW Voltage (Note 21)
−3.465 V V
EE
−3.0 V
(OLS = V
CC
)
(OLS = V
CC
− 0.4 V)
(OLS = V
CC
− 0.8 V, OLS = FLOAT)
(OLS = V
CC
− 1.2 V)
**(OLS = V
EE
)
−3.0 V < V
EE
−2.375 V
(OLS = V
CC
)
(OLS = V
CC
− 0.4 V)
(OLS = V
CC
− 0.8 V, OLS = FLOAT)
(OLS = V
CC
− 1.2 V)
(OLS = V
EE
)
−1980
−1270
−1750
−1040
−1515
−1945
−1265
−1725
−1045
−1495
−1830
−1210
−1630
−990
−1425
−1795
−1205
−1605
−995
−1405
−1680
−1150
−1510
−940
−1335
−1645
−1145
−1485
−945
−1315
−1940
−1235
−1715
−1010
−1480
−1905
−1230
−1690
−1010
−1460
−1790
−1175
−1595
−960
−1390
−1755
−1170
−1570
−960
−1370
−1640
−1115
−1475
−910
−1300
−1605
−1110
−1450
−910
−1280
−1910
−1210
−1685
−985
−1450
−1875
−1205
−1660
−990
−1435
−1760
−1150
−1565
−935
−1360
−1725
−1145
−1540
−940
−1345
−1610
−1090
−1445
−885
−1270
−1575
−1085
−1420
−890
−1255
mV
V
OUTPP
Output Voltage Amplitude
−3.465 V V
EE
−3.0 V
(OLS = V
CC
)
(OLS = V
CC
− 0.4 V)
(OLS = V
CC
− 0.8 V, OLS = FLOAT)
(OLS = V
CC
− 1.2 V)
**(OLS = V
EE
)
−3.0 V < V
EE
−2.375 V
(OLS = V
CC
)
(OLS = V
CC
− 0.4 V)
(OLS = V
CC
− 0.8 V, OLS = FLOAT)
(OLS = V
CC
− 1.2 V)
(OLS = V
EE
)
750
130
550
0
345
715
125
525
0
325
840
220
640
0
435
805
215
615
5
415
740
125
545
0
340
705
120
520
0
320
830
215
635
0
430
795
210
610
0
410
735
125
540
0
335
700
120
515
0
320
825
215
630
0
425
790
210
605
5
410
mV
V
IH
Input HIGH Voltage (Single−Ended)
(Note 23) D, D
V
EE
+
1275
V
CC
−
1000*
V
CC
V
EE
+
1275
V
CC
−
1000*
V
CC
V
EE
+
1275
V
CC
−
1000*
V
CC
mV
V
IL
Input LOW Voltage (Single−Ended)
(Note 24) D, D
V
IH
−
2600
V
CC
−
1400*
V
IH
−
150
V
IH
−
2600
V
CC
−
1400*
V
IH
−
150
V
IH
−
2600
V
CC
−
1400*
V
IH
−
150
mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 22)
V
EE
+1.2 0.0 V
EE
+1.2 0.0 V
EE
+1.2 0.0 V
R
TIN
Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55
I
IH
Input HIGH Current (@V
IH
) D, D
SEL
30
5
100
50
30
5
100
50
30
5
100
50
A
I
IL
Input LOW Current (@V
IL
) D, D
SEL
20
5
100
50
20
5
100
50
20
5
100
50
A
NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
20.Input and output parameters vary 1:1 with V
CC
.
21.All loading with 50 to V
CC
− 2.0 V.
22.V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
23.V
IH
cannot exceed V
CC
.
24.V
IL
always V
EE
.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and V
CC
− V
EE
> 3.0 V, a 2 k resistor should be connected from OLS to V
EE
.
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have
maximum ambient temperature specification of 85°C.
NBSG86A
http://onsemi.com
9
Table 13. AC CHARACTERISTICS for FCBGA−16
V
CC
= 0 V; V
EE
= −3.465 V to −2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
−40°C 25°C 70°C
Symbol Characteristic
Min Typ Max Min Typ Max Min Typ Max
Unit
f
max
Maximum Frequency
(See Figure 8) (Note 25)
7 8 7 8 7 8 GHz
V
OUTPP
Output Voltage Amplitude
(OLS = V
CC
)f
in
7 GHz 550 740 500 720 450 700 mV
t
PLH
,
t
PHL
Propagation Delay to Output Differential
D/SEL → Q 110 160 210 115 165 215 120 170 220
ps
t
SKEW
Duty Cycle Skew (Note 26) 5 15 5 15 5 15 ps
t
SKEW
Channel Skew Q → D/SEL 5 20 5 20 5 20 ps
t
JITTER
RMS Random Clock Jitter
(See Figure 8) (Note 25)
f
in
7 GHz
Peak−to−Peak Data Dependent Jitter
f
in
7 Gb/s
0.5
12
1.5 0.5
12
1.5 0.5
12
1.5
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 27)
75 2600 75 2600 75 2600 mV
t
r
t
f
Output Rise/Fall Times (20% − 80%) (Q, Q)
@ 1 GHz 20 40 65 20 40 65 20 40 65
ps
25.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 to V
CC
− 2.0 V. Input edge rates 40 ps (20% − 80%).
26.t
SKEW
= |t
PLH
− t
PHL
| for a nominal 50% differential clock input waveform. See Figure 12.
27.V
INPP
(max) cannot exceed V
CC
− V
EE
.
Table 14. AC CHARACTERISTICS for QFN−16
V
CC
= 0 V; V
EE
= −3.465 V to −2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
−40°C 25°C 85°C
Symbol Characteristic
Min Typ Max Min Typ Max Min Typ Max
Unit
f
max
Maximum Frequency
(See Figure 8) (Note 28)
7 8 7 8 7 8 GHz
V
OUTPP
Output Voltage Amplitude f
in
7 GHz
(OLS = V
CC
)f
in
= 8 GHz
590
270
730
440
470
230
720
420
540
180
700
390
mV
mV
t
PLH
,
t
PHL
Propagation Delay to Output Differential
D/SEL → Q 110 160 210 115 165 215 120 170 220
ps
t
SKEW
Duty Cycle Skew (Note 29) 5 15 5 15 5 15 ps
t
SKEW
Channel Skew Q → D/SEL 5 20 5 20 5 20 ps
t
JITTER
RMS Random Clock Jitter
(See Figure 8) (Note 31)
f
in
7 GHz
Peak−to−Peak Data Dependent Jitter
(Note 32) f
in
7 Gb/s
0.5
12
1.5 0.5
12
1.5 0.5
12
1.5
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 30)
75 2600 75 2600 75 2600 mV
t
r
t
f
Output Rise/Fall Times (20% − 80%) (Q, Q)
t
r
@ 1 GHz t
f
30
17
45
35
60
65
30
17
45
35
60
65
30
17
45
35
60
65
ps
28.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 to V
CC
− 2.0 V. Input edge rates 40 ps (20% − 80%).
29.t
SKEW
= |t
PLH
− t
PHL
| for a nominal 50% differential clock input waveform. See Figure 12.
30.V
INPP
(max) cannot exceed V
CC
− V
EE
.
31.Additive RMS jitter with 50% duty cycle clock signal at 7 GHz.
32.Additive Peak−to−Peak data dependent jitter with NRZ PRBS 2
31
−1 data rate at 7 Gb/s.
P1-P3P4-P6P7-P9P10-P12P13-P14

NBSG86ABAEVB

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Manufacturer:
ON Semiconductor
Description:
Clock & Timer Development Tools BBG NBSG86ABA EVAL BOARD
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