NBSG86A
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5
Table 7. Interfacing Options
INTERFACING OPTIONS CONNECTIONS
CML Connect VTD0, VTD1, VTSEL and VTD0, VTD1 to V
CC
LVDS Connect VTD0, VTD1, VTD0 and VTD1 together. Leave VTSEL open.
AC−COUPLED Bias VTD0, VTD1, VTSEL and VTD0, VTD1 Inputs within (VIHCMR) Common Mode Range
RSECL, PECL, NECL Standard ECL Termination Techniques
LVTTL, LVCMOS An external voltage should be applied to the unused complementary differential input.
Nominal voltage 1.5 V for LVTTL and V
CC
/2 for LVCMOS inputs.
Table 8. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistors (R
1
) 75 k
Internal Input Pullup Resistor (R
2
) 37.5 k
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 1 KV
> 50 V
> 4 KV
Moisture Sensitivity (Note 6) 16−FCBGA
16−QFN
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 364
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
Table 9. MAXIMUM RATINGS (Note 7)
Symbol
Parameter Condition 1 Condition 2 Rating Units
V
CC
Positive Power Supply V
EE
= 0 V 3.6 V
V
EE
Negative Power Supply V
CC
= 0 V −3.6 V
V
I
Positive Input
Negative Input
V
EE
= 0 V
V
CC
= 0 V
V
I
V
CC
V
I
V
EE
3.6
−3.6
V
V
V
INPP
Differential Input Voltage |D
n
− D
n
| V
CC
− V
EE
2.8 V
V
CC
− V
EE
< 2.8 V
2.8
|V
CC
− V
EE
|
V
V
I
IN
Input Current Through R
T
(50 Resistor) Static
Surge
45
80
mA
mA
I
out
Output Current Continuous
Surge
25
50
mA
mA
TA Operating Temperature Range 16−FCBGA
16−QFN
−40 to +70
−40 to +85
°C
°C
T
stg
Storage Temperature Range −65 to +150 °C
JA
Thermal Resistance (Junction−to−Ambient)
(Note 8)
0 LFPM
500 LFPM
0 LFPM
500 LFPM
16 FCBGA
16 FCBGA
16 QFN
16 QFN
108
86
41.6
35.2
°C/W
°C/W
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case) 2S2P (Note 8)
2S2P (Note 9)
16 FCBGA
16 QFN
5.0
4.0
°C/W
°C/W
T
sol
Wave Solder 15 Sec. 225 °C
7. Maximum Ratings are those values beyond which device damage may occur.
8. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
9. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
