NCV7510
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16
DETAILED OPERATING DESCRIPTION (continued)
Bits D
4
-D
0
of the 16-bit SO word indicate detected faults
such that D
X
= 1 when a fault is detected. Figure 16 describes
the fault bit definitions. At POR, the register bits are cleared
to $00. Refer to the Fault Diagnosis description for details
regarding the NCV7510's fault strategies and behaviors,
discussed in the next section.
D
4
D
3
D
2
D
1
D
0
SO FAULT DATA
OVERVOLTAGE
SHORT TO GND SHORT TO BATTERY
OPEN LOAD
OVERCURRENT
D
15
- D
5
= DON'T CARE; D
4
- D
0
: 1 = FAULT, 0 = NO FAULT
Figure 16. SO Fault Bit Definitions
Fault Diagnosis and Protection Behavior
General
The NCV7510 continuously monitors the load supply
voltage, external MOSFETs, the load current, and the
control loop state during a control cycle for fault conditions.
Faults are managed on a cycle-by-cycle basis with regard
to the CONTROL and ENA inputs and are recoverable
(automatic fault re-try) such that the NCV7510 will attempt
to properly drive the load during the next control cycle.
Attention is focused on faults that may cause destructive
failure of the load, the external MOSFETs, or the sense
resistor.
Overcurrent faults are detectable regardless of the
CONTROL and ENA input states. Short to battery and short
to GND (antisaturation) faults are detectable when the
CONTROL and ENA inputs are high. Destructive fault
types are managed when possible to prevent failure by
latching both predriver outputs off. Fault reporting for these
types is priority encoded such that the first detected fault
locks out subsequent fault reporting bits. These faults cause
the FAULT flag to be set and latched low.
Non-destructive open load faults require no intervention
and are detectable at the end of a control cycle when
CONTROL or ENA goes low. This fault type has no priority
and is reported if no other fault has been detected, and does
not set the FAULT flag.
Overvoltage faults are detected without regard to the
CONTROL and ENA inputs. Management, reporting and
FAULT flag behavior for this fault type is dependent upon
the state of AUX register bit D
6
.
Reset of fault protection, and clearing of fault data and the
FAULT flag are independent. Protection circuitry is reset on
the rising edge of either the CONTROL or ENA inputs.
Fault data and the FAULT flag are cleared by the rising edge
of CSB. At power-on reset, all fault protection, fault data,
and the FAULT flag are cleared.
Fault detection, protection and reporting are detailed in
the following sections and are summarized in Table 1.
Overvoltage
The load supply voltage is monitored at the DRN pin for
overvoltage faults, and fault detection occurs regardless of
the states of CONTROL and ENA inputs. The interruption
of load current by the overvoltage detection circuit can be
programmed by bit D
6
in the AUX register. At POR, the
overvoltage interrupt default state is disabled (AUX D
6
=0).
When AUX D
6
=0 an overvoltage fault has no priority and
is reported if no other fault has been detected. The predrivers
and the FAULT flag are unaffected.
Programming AUX D
6
=1 enables overvoltage interrupt.
When CONTROL and ENA are high, an overvoltage fault
will cause the GATE output to be latched off, the CLAMP
output to be latched on, and the FAULT flag to be latched
low. The fault is given reporting priority and locks out
subsequent fault reporting bits. Overvoltage protection is
reset when CONTROL or ENA is brought low and then high
again.
Avalanche of the high side (HS) MOSFET may occur
when the CLAMP MOSFET is on during an overvoltage
fault (overvoltage enabled.) Avalanche of both the HS and
CLAMP MOSFETs may occur (overvoltage disabled) if the
overvoltage amplitude exceeds the combined avalanche
voltages of both MOSFETs. The devices should be carefully
chosen for proper avalanche voltage and avalanche energy
rating suitable to the application and its operating
environment.
Note that the NCV7510 requires transient overvoltage
suppression in accordance with the specifications in the
Maximum Ratings table.
Overcurrent
Load current (converted to a voltage by external sense
resistor R
SNS
) is monitored at the SNS+ and SNS-
differential inputs. A fault is detected when the amplified
differential voltage exceeds the overcurrent reference. A
nominal 2.5 ms filter is used to help prevent false overcurrent
detection.
Overcurrent detection occurs regardless of the states of
the CONTROL and ENA inputs. This fault has reporting
priority and will latch the FAULT flag low. If overcurrent is
detected when CONTROL and ENA are high, both GATE
and CLAMP outputs are latched off. Overcurrent protection
is reset when the CONTROL or ENA input is brought low
and then high again.
