NCV7510
http://onsemi.com
5
PIN FUNCTION DESCRIPTIONS
ENA: CMOS input with hysteresis logically ANDed with
the CONTROL input to command the predriver outputs.
This input has an active pulldown current source.
CONTROL: CMOS input with hysteresis logically ANDed
with the ENA input to command the predriver outputs. This
input has an active pulldown current source.
PCLK: Buffered CMOS input with hysteresis. This input
controls which DAC register pair is selected for load current
comparison. The input is programmed via Auxiliary register
($01) bit D
3
to respond to a clock signal (AUX D
3
=0 default
at POR) or a logic level (AUX D
3
=1.) The pin presents a
12 pF maximum load to the controller.
CSB: CMOS input with hysteresis. This input is the
active-low chip select input that enables serial data transfer
between the host controller and the device. This input has an
active pullup current source.
SCLK: Buffered CMOS input with hysteresis. This input
is the synchronizing clock input for serial data transfer
between the micro controller and the device. The pin
presents a 12 pF maximum load to the controller.
SI: Buffered CMOS input with hysteresis. This pin is the
data input to the device's SPI shift register. Serial data
received at this input is transferred from the host controller
to the shift register under the control of the CSB and SCLK
inputs. The pin presents a 12 pF maximum load to the
controller. This input has an active pulldown current source.
SO: The CMOS compatible line driver at this pin is the data
output from the device's SPI shift register. Serial data
transmitted at this output is transferred from the shift register
to the host controller under the control of the CSB and SCLK
inputs. The pin is capable of driving 200 pF at 4 MHz and
is HI-Z when the CSB input is high.
LOOP: The CMOS compatible driver at this pin reflects the
state of the control loop. A logic low indicates that load
current is less than the programmed DAC reference.
FAULT: An open-drain low voltage NMOS output at this
pin provides immediate fault indication to a connected host
controller. An external resistor is normally connected
between this pin and V
DD
.
DGND: Device substrate voltage and V
DD
return path for
mixed signal functions. This pin is the circuit common
reference point.
OCP: This analog comparator input supplies a reference
voltage to the device's overcurrent fault detection. When the
voltage at this pin is less than 4.5 V, the applied voltage is the
overcurrent reference voltage. When the voltage is greater
than 4.5 V, an internal 3.0 V overcurrent reference is used.
The voltage at this pin must not exceed V
DD
. Applying
approximately V
DD
+ 1.4 V will place the NCV7510 in test
mode and suspend normal operation. The user is advised to
avoid activating the test mode.
V
DD
: +5.0 Vpower supply input. The voltage at this pin
initiates power-on reset, supplies power to internal
mixed-signal functions and supplies gate charge to the
external CLAMP MOSFET. A low ESR external bulk
capacitor connected between V
DD
and PGND is
recommended to supply transient gate charge. Several
internal reference voltages are derived from V
DD
.
SNS-: The inverting input to the analog current sense
amplifier. This input should be Kelvin connected directly to
the external current sense resistor's negative terminal.
SNS+: The noninverting input to the analog current sense
amplifier. This input should be Kelvin connected directly to
the external current sense resistor's positive terminal.
PGND: Return path for the GATE and CLAMP predriver
transient currents and the lower input to the CLAMP
antisaturation detection comparator. This pin should be
star-connected to the CLAMP MOSFET's source and the
external V
DD
bulk charge capacitor's negative terminal.
CLAMP: External CLAMP MOSFET predrive output.
This output switches the CLAMP MOSFET's gate between
V
DD
and PGND.
SRC: Lower input to the GATE antisaturation detection
comparator and upper input to the CLAMP antisaturation
detector.
GATE: External HS MOSFET predrive output. This output
switches the HS MOSFET's gate between V
B
and PGND.
DRN: Upper input to the GATE antisaturation detection
comparator, overvoltage detection input, and powerup
interlock input. This pin should be connected directly to the
HS MOSFET's drain terminal.
VB: Bootstrap or boost input voltage. This input supplies
gate charge to the external HS MOSFET.
