NCV7510
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7
ELECTRICAL CHARACTERISTICS (5 V < V
DRN
< 26 V, 4.75 V < V
DD
< 5.25 V, -40°C < T
J
< 125°C, unless otherwise specified.)
(Note 4)
Characteristic Conditions Min Typ Max Unit
DRN Input
Input Current V
DRN
= 12.8 V, V
DD
= 0 V
V
DRN
= 26 V, V
DD
=5.25 V
-
0.5
5.0
2.0
mA
mA
Power-On Lockout Threshold V
DD
= 0 V, GATE predriver locked out 0.7 1.5 V
Over-Voltage Lockout GATE predriver disabled, CLAMP predriver active
Auxiliary Register Bit 6 = 1
28 32 36 V
Over-Voltage Hysteresis 0.1 0.8 2.0 V
V
B
Input
Input Bias Current V
B
= 24 V 0.7 1.5 mA
V
DD
Supply
Operating Current V
DRN
= 14 V 3.5 7.0 mA
Power-On Reset Threshold Predrivers disabled, V
DD
rising 3.0 3.5 4.4 V
Power-On Reset Hysteresis - 0.25 - V
Digital I/O
V
IN
High ENA, CONTROL, SI, SCLK, CSB, PCLK 2.2 V
V
IN
Low ENA, CONTROL, SI, SCLK, CSB, PCLK 0.8 V
V
IN
Hysteresis ENA, CONTROL, SI, SCLK, CSB, PCLK 0.6 1.2 V
Input Pulldown Current ENA, CONTROL, SI: V
IN
= V
DD
25
mA
Input Pullup Current CSB: V
IN
= 0 V -25
mA
SO Low Voltage I
SINK
= 1 mA 0.4 V
SO High Voltage I
SOURCE
= 1 mA V
DD
- 1.0 V
LOOP Low Voltage I
SINK
= 0.1 mA 0.5 V
LOOP High Voltage I
SOURCE
= 0.1 mA V
DD
- 1.0 V
LOOP Output Response Delay
(See Figure 3)
t
LOOP(HL)
; C
LOOP
= 50 pF
t
LOOP(LH)
; C
LOOP
= 50 pF
0.5
0.5
1.2
1.2
ms
ms
FAULT Low Voltage FAULT Active, I
FAULT
= 0.5 mA 0.1 0.5 V
PCLK Input
Input Capacitance (Note 5) 12 pF
Clock Frequency Auxiliary Register Bit 3 = 0 (Note 5) 0 20 MHz
DAC Reference Select Delay Auxiliary Register Bit 3 = 1 (Note 5) 3.0
ms
NCV7510
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8
ELECTRICAL CHARACTERISTICS (continued) (5 V < VDRN < 26 V, 4.75 V < V
DD
< 5.25 V, -40°C < T
J
< 125°C, unless
otherwise specified.) (Note 4)
Characteristic Conditions Min Typ Max Unit
GATE and CLAMP Predrivers
GATE Output R
DS(ON)
High V
B
= 7.3 V, V
B
-V
GATE
= 0.5 V 20 50
W
GATE Output R
DS(ON)
Low V
B
= 7.3 V, V
GATE
= 0.5 V 20 50
W
GATE Output Delay
(See Figure 4)
t
P(LH)
; ENA or CONTROL High to GATE High
C
GATE
=2 nF
0.8 1.6
ms
t
P(HL)
; ENA or CONTROL Low to GATE Low
C
GATE
=2 nF
0.3 0.6
ms
GATE Response Delay
(See Figure 4)
t
DLY(GR)
;SNS+ Falling to GATE Rising
V
DD
=5.0 V, VDRN=10 V, V
B
=20 V,
V
SRC
Following V
GATE
, V
DAC
=20% FS, C
GATE
=2 nF
0.4 1.6
ms
t
DLY(GF)
;SNS+ Rising to GATE Falling
V
DD
=5.0 V, VDRN=10 V, V
B
=20 V,
V
SRC
Following V
GATE
, V
DAC
=80% FS, C
GATE
=2 nF
0.4 1.6
ms
GATE Output Low Hold Time
(See Figure 5)
V
DD
= 5.0 V, C
GATE
=2 nF 5.0 10 15
ms
GATE Output Pulldown (HI-Z) 20 60 150
kW
CLAMP Output R
DS(ON)
High V
DD
= 5.0 V, V
DD
-V
CLAMP
= 0.5 V 20 50
W
CLAMP Output R
DS(ON)
Low V
DD
= 5.0 V, V
CLAMP
= 0.5 V 20 50
W
CLAMP Output Pulldown 50 200 500
kW
CLAMP Output Delay ENA or CONTROL Input Low to CLAMP Output Low;
(Note 5)
3.0
ms
Current Sense Amplifier
Input Bias current SNS+, SNS- = 0 V (Each Input) -5.0 -
mA
Input Common Mode Range
DV
(SNS+,SNS-)
=750 mV
-0.3 1.0 V
Current Sense Conversion (V
DD
= 5.0 V)
D/A Resolution Referred to SNS+, SNS- Inputs 4.70 4.92 5.20 mV
Full Scale Value Referred to SNS+, SNS- Inputs 575 625 675 mV
Differential Non-Linearity - ±0.75 LSB
DAC Offset DAC Code = 0 -5.0 - 5.0 mV
Trip Point Accuracy DAC Code = 32
10
(25% FS) –12.5 - 12.5 mV
DAC Code = 66
10
(50% FS) –12.5 - 12.5 mV
DAC Code = 95
10
(75% FS) –12.5 - 12.5 mV
DAC Response Delay
(See Figure 6)
t
DAC
; CSB Rising to LOOP State Change
DAC Code = 127
10
(Full Scale)
C
GATE
= 2 nF (Note 5)
- 500 ns
NCV7510
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9
ELECTRICAL CHARACTERISTICS (continued) (5 V < VDRN < 26 V, 4.75 V < V
DD
< 5.25 V, -40°C < T
J
< 125°C, unless
otherwise specified.) (Note 4)
Characteristic Conditions Min Typ Max Unit
Overcurrent Comparator
Input Bias Current V
OCP
= 3.0 V 0.26 3.0
mA
Linear Input Voltage Range 1.0 3.0 V
Mode Select Threshold V
DD
= 5.0 V 4.2 4.5 4.8 V
Internal Overcurrent Reference V
OCP
= V
DD
= 5.0 V 2.7 3.0 3.3 V
Detection Blanking Time
(See Figure 7)
Time to FAULT output low 1.25 2.5 5.0
ms
Antisaturation Detect
GATE MOSFET Auxiliary Register Bit 5 = 0, VDRN-V
SRC
Auxiliary Register Bit 5 = 1, VDRN-V
SRC
0.96
1.92
1.20
2.40
1.44
2.88
V
V
CLAMP MOSFET Auxiliary Register Bit 4 = 0, V
SRC
-V
PGND
Auxiliary Register Bit 4 = 1, V
SRC
-V
PGND
0.2
0.4
0.4
0.8
0.6
1.2
V
V
SRC Input Bias Current V
SRC
= 14 V, V
GATE
= 14 V
V
SRC
= 0 V, V
GATE
= 0 V
-10
0.44
4.0
mA
mA
Detection Blanking Time
(See Figure 8)
Time to FAULT output low; GATE or CLAMP 5.0 10 20
ms
Serial Peripheral Interface (VDRN = 14 V, V
DD
= 5.0 V, C
so
= 200 pF) (Figure 9)
SCLK Clock Period 250 ns
Maximum Input Capacitance Sl, SCLK; (Note 5) 12 pF
SCLK High Time f
sclk
= 4.0 MHz, SCLK = 2.0 V to 2.0 V 125 ns
SCLK Low Time f
sclk
= 4.0 MHz. SCLK = 0.8 V to 0.8 V 125 ns
Sl Setup Time Sl = 0.8 V/2.0 V to SCLK = 2.0 V
f
SCLK
= 4.0 MHz (Note 5)
25 ns
Sl Hold Time SCLK = 2.0 V to Sl = 0.8 V/2.0 V
f
SCLK
= 4.0 MHz (Note 5)
25 ns
SO Rise Time (10% V
SO
to 90% V
DD
)
C
so
= 200 pF (Note 5)
25 50 ns
SO Fall Time (90% V
SO
to 10% V
DD
)
C
so
= 200 pF (Note 5)
50 ns
CSB Setup Time CSB = 0.8 V to SCLK = 2.0 V
(Note 5)
60 ns
CSB Hold Time SCLK = 0.8 V to CSB = 2.0 V
(Note 5)
75 ns
SO Delay Time SCLK = 0.8 V to SO Data Valid
f
SCLK
= 4.0 MHz (Note 5)
65 125 ns
Transfer Delay Time CSB rising edge to next falling edge.
(Note 5)
1.0
ms
4. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100%
parametrically tested in production.
5. Guaranteed by design.

NCV7510DWR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers OSPI PRE-DRIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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