RESETIN Input (MAX16998A/B/D)
The MAX16998A/B/D monitor the voltage at RESETIN
using an adjustable reset threshold, set with an external
resistive divider (see Figure 7). RESET asserts when
V
RESETIN
is below 1.235V.
Use the following equations to calculate the externally
monitored voltage (V
CC
).
where V
TH
is the desired reset threshold voltage, and
V
PON
= 1.235V. To simplify the resistor selection,
choose a value for R
2
(< than 1MΩ) and calculate R
1
.
EN Input
The MAX16997A provides a high-impedance input (EN)
to the enable comparator. Based on the voltage level at
EN, the watchdog timer is turned on or off. The watch-
dog timer starts timing if the voltage level at EN is high-
er than a preset threshold voltage (V
PON
). Each time
the voltage at EN rises from below to above the preset
threshold voltage, the initial watchdog timeout period is
8 times the normal watchdog timeout period (t
WP
).
Watchdog Timer
MAX16997A
The watchdog circuit monitors the µC’s activity. For the
MAX16997A, the watchdog timer starts timing once the
voltage at EN is higher than a preset threshold voltage.
ENABLE asserts if three consecutive watchdog timeout
periods have elapsed without a falling edge at WDI.
ENABLE remains low until three consecutive WDI falling
edges with periods shorter than the watchdog timeout
period occur.
Each time the voltage at EN rises from below to above
the preset threshold voltage, the first watchdog timeout
period extends by a factor of 8 (8 x t
WP
). If a WDI falling
edge occurs during that time, then the watchdog time-
out period is immediately switched over to a single t
WP
.
If no watchdog falling edge occurs during this pro-
longed watchdog timeout period, ENABLE goes low at
the end of this period and stays low. After this, the first
falling edge at WDI switches the watchdog timeout
period to a single t
WP
. See Figure 1. The MAX16997A
watchdog timeout period (t
WP
) is adjustable by a single
capacitor at SWT.
MAX16998A
The MAX16998A asserts RESET when two consecutive
WDI falling edges do not occur within the adjusted
watchdog timeout period (t
WP
). RESET remains assert-
ed for the reset timeout period (t
RESET
) and then goes
high. This device also asserts ENABLE if three consec-
utive watchdog timeout periods have elapsed without a
falling edge at WDI. ENABLE remains low until three
consecutive WDI falling edges with periods shorter
than the watchdog timeout period occur (see Figure 2).
The internal watchdog timer is cleared by a RESET ris-
ing edge or by a falling edge at WDI. The watchdog
timer remains cleared while RESET is asserted; as soon
as RESET is released, the timer starts counting. WDI
falling edges are ignored when RESET is low. If no WDI
falling edge occurs within the watchdog timeout period,
RESET immediately goes low and stays low for the
adjusted reset timeout period.
MAX16998B/D
The MAX16998B/D have a windowed watchdog timer.
The watchdog timeout period (t
WP
) is the sum of a
closed window period (t
CW
) and an open window period
(t
OW
). If the µC issues a WDI falling edge within the open
window period, RESET stays high. Once a WDI falling
edge occurs within the closed window period, RESET
immediately goes low and stays low for the adjusted
reset timeout period (see Figure 3). If no WDI falling
edge occurs within the watchdog timeout period, RESET
immediately goes low and stays low for the adjusted
reset timeout period. The open window size is factory-set
to 50% of the watchdog timeout period for the
MAX16998B and 75% for the MAX16998D.
Figure 8 shows a WDI falling edge identified as a
good
or
a
bad
WDI signal edge. In case 1, the WDI falling edge
occurs within the closed window period and is considered
a
bad
WDI falling edge (early fault); therefore, it asserts
RESET. Case 2 also shows another fault. In this case, no
