MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
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Pin Description
PIN
MAX16997A MAX16998A/B/D
NAME FUNCTION
1 1 IN Power-Supply Input. Bypass IN to GND with a 0.1µF capacitor.
2—EN
High-Impedance Input to the Enable Comparator. Depending on the voltage level
at EN, the internal watchdog timer is turned on or off (see the EN Input section).
3, 7 — N.C. No Connection. Not internally connected.
44SWT
Watchdog Timeout Adjustment Input. Connect a capacitor between SWT and GND
to set the basic watchdog timeout period. Connect SWT to ground to disable the
watchdog timer function. See the Selecting the Watchdog Timeout Capacitor
section.
5 5 GND Ground
6 6 WDI
Watchdog Input.
MAX16997A/MAX16998A (Timeout Watchdog): Two consecutive WDI falling
edges must occur at WDI within the watchdog timeout period or RESET asserts.
The watchdog timer clears when a falling edge occurs on WDI or whenever RESET
is asserted. ENABLE asserts if three consecutive watchdog timeout periods have
expired without a falling edge at WDI. WDI is a high-impedance input. Leaving
WDI unconnected will cause improper operation of the watchdog timer.
MAX16998B/D (Window Watchdog): WDI falling transitions within periods shorter
than the closed window width or longer than the basic watchdog timeout period
force RESET to assert low for the reset timeout period. The watchdog timer begins
to count after RESET is deasserted. The watchdog timer clears when a WDI falling
edge occurs or whenever RESET is asserted. ENABLE asserts if three consecutive
watchdog timeout periods have expired without a falling edge at WDI. WDI is a
high-impedance input. Leaving WDI unconnected will cause improper operation of
the watchdog timer.
88ENABLE
Open-Drain Enable Output. ENABLE asserts when three consecutive WDI faults
occur. ENABLE remains low until three consecutive good WDI falling edges occur.
ENABLE does not assert if the voltage at RESETIN (EN) is below its threshold.
These devices are guaranteed to be in correct ENABLE output logic state when
V
IN
remains greater than 1.1V.
— 2 RESETIN
Reset Input. High-impedance input to the reset comparator. When V
RESETIN
falls
below 1.235V, RESET asserts. RESET remains asserted as long as V
RESETIN
is low
and for the reset timeout period after RESETIN goes high. Connect V
RESETIN
to the
center point of an external resistive divider to set the threshold for the externally
monitored voltage. Connect RESETIN to a defined voltage logic-level.
— 3 SRT
Reset Timeout Adjustment Input. Connect a capacitor between SRT and GND to
set the reset timeout period. See the Selecting the Reset Timeout Capacitor
section.
—7RESET
Open-Drain Reset Output. RESET asserts whenever RESETIN drops below the
selected reset threshold voltage (V
PON
). RESET remains low for the reset timeout
period after all reset conditions are removed, and then goes high. RESET asserts
for a period of t
RESET
whenever a WDI fault occurs. Connect RESET to a pullup
resistor connected to a voltage higher than 2.5V (typ).
