LTC3260
10
3260fa
operaTion
(Refer to the Block Diagram)
Figure 2 shows the LDO
+
regulator application circuit.
The LDO
+
output voltage V
LDO
+
can be programmed by
choosing suitable values of R1 and R2 such that:
V
LDO
+
=1.2V
R1
R2
+1
An optional capacitor of 10nF can be connected from the
BYP
+
pin to ground. This capacitor bypasses the internal
1.2V reference of the LTC3260 and improves the noise
performance of the LDO
+
. If this function is not used the
BYP
+
pin should be left floating.
negative by the charge pump circuitry. Soft-start circuitry
in the charge pump also provides soft-start functionality
for the LDO
and prevents excessive inrush currents.
Figure 3 shows the LDO
regulator application circuit.
The LDO
output voltage V
LDO
can be programmed by
choosing suitable values of R1 and R2 such that:
V
LDO
= –1.2V
R1
R2
+1
When the inverting charge pump is in Burst Mode opera-
tion (MODE = high), the typical hysteresis on the V
OUT
pin is 2% of V
IN
voltage. The LDO
voltage should be set
high enough above V
OUT
in order to prevent LDO
from
entering dropout during normal operation.
An optional capacitor of 10nF can be connected from the
BYP
pin to ground. This capacitor bypasses the internal
–1.2V reference of the LTC3260 and improves the noise
performance of the LDO
. If this function is not used the
BYP
pin should be left floating.
In order to improve transient response, an optional
capacitor, C
ADJ
, may be used as shown in Figure 3. A
recommended value for C
ADJ
is 10pF. Experimentation
with capacitor values between 2pF and 22pF may yield
improved transient response.
Figure 2: Positive LDO Application Circuit
V
IN
1
0
LDO
+
EN
+
ADJ
+
GND
BYP
+
C
BYP
+
C
OUT
LTC3260
LDO
OUTPUT
R2
3260 F02
R1
1.2V
REF
Figure 3: Negative LDO Application Circuit
V
OUT
1
0
LDO
EN
ADJ
GND
BYP
C
BYP
C
ADJ
C
OUT
3260 F03
LTC3260
LDO
OUTPUT
R2
R1
–1.2V
REF
Negative Low Dropout Linear Regulator (LDO
)
The negative low dropout regulator (LDO
) supports a
load of up to 50mA. The LDO
takes power from the V
OUT
pin (output of the inverting charge pump) and drives the
LDO
output pin to a voltage programmed by the resis-
tor divider connected between the LDO
, ADJ
and GND
pins. For stability, the LDO
output must be bypassed to
ground with a low ESR ceramic capacitor that maintains a
capacitance of at leastF across operating temperature
and voltage.
The LDO
is enabled or disabled via the EN
logic input
pin. Initially, when the EN
logic input is low, the charge
pump circuitry is disabled and the V
OUT
pin is at GND.
When EN
is switched high, the V
OUT
pin will be driven
LTC3260
11
3260fa
applicaTions inForMaTion
Effective Open-Loop Output Resistance
The effective open-loop output resistance (R
OL
) of a charge
pump is a very important parameter which determines the
strength of the charge pump. The value of this parameter
depends on many factors such as the oscillator frequency
(f
OSC
), value of the flying capacitor (C
F LY
), the nonoverlap
time, the internal switch resistances (R
S
) and the ESR of
the external capacitors.
Typical R
OL
values as a function of temperature are shown
in Figure 4
minimum turn-on time. The peak-to-peak output ripple at
the V
OUT
pin is approximately given by the expression:
V
RIPPLE(P-P)
I
OUT
C
OUT
1
f
OSC
t
ON
where C
OUT
is the value of the output capacitor, f
OSC
is the
oscillator frequency and t
ON
is the on-time of the oscillator
(1µs typical).
Just as the value of C
OUT
controls the amount of output
ripple, the value of C
IN
controls the amount of ripple present
at the input (V
IN
) pin. The amount of bypass capacitance
required at the input depends on the source impedance
driving V
IN
. For best results it is recommended that V
IN
be bypassed with at leastF of low ESR capacitance. A
high ESR capacitor such as tantalum or aluminum will
have higher input noise than a low ESR ceramic capacitor.
Therefore, a ceramic capacitor is recommended as the
main bypass capacitance with a tantalum or aluminum
capacitor used in parallel if desired.
Flying Capacitor Selection
The flying capacitor controls the strength of the charge
pump. AF or greater ceramic capacitor is suggested
for the flying capacitor for applications requiring the full
rated output current of the charge pump.
For very light load applications, the flying capacitor may
be reduced to save space or cost. For example, a 0.2µF
capacitor might be sufficient for load
currents up to 20mA.
A
smaller flying capacitor leads to a larger effective open-
loop resistance (R
OL
) and thus limits the maximum load
current that can be delivered by the charge pump.
Ceramic Capacitors
Ceramic capacitors of different materials lose their capaci-
tance with higher temperature and voltage at different rates.
For example, a capacitor made of X5R or X7R material
will retain most of its capacitance from –40°C to 85°C
whereas a Z5U or Y5V style capacitor will lose considerable
capacitance over that range. Z5U and Y5V capacitors may
Figure 4. Typical R
OL
vs Temperature
Input/Output Capacitor Selection
The style and value of capacitors used with the LTC3260
determine several important parameters such as regulator
control loop stability, output ripple, charge pump strength
and minimum turn-on time. To reduce noise and ripple,
it is recommended that low ESR ceramic capacitors be
used for the charge pump and LDO outputs. All capacitors
should retain at leastF of capacitance over operating
temperature and bias voltage. Tantalum and aluminum
capacitors can be used in parallel with a ceramic capacitor
to increase the total capacitance but should not be used
alone because of their high
ESR. In constant frequency
mode,
the value of C
OUT
directly controls the amount of
output ripple for a given load current. Increasing the size of
C
OUT
will reduce the output ripple at the expense of higher
TEMPERATURE (°C)
50
0
EFFECTIVE OPEN-LOOP RESISTANCE (Ω)
10
20
30
40
0 50
100
150
3620 F04
50
60
25 25
75
125
V
IN
= 32V
V
IN
= 25V
V
IN
= 12V
f
OSC
= 500kHz
LTC3260
12
3260fa
applicaTions inForMaTion
also have a poor voltage coefficient causing them to lose
60% or more of their capacitance when the rated voltage
is applied. Therefore when comparing different capacitors,
it is often more appropriate to compare the amount of
achievable capacitance for a given case size rather than
discussing the specified capacitance value. The capacitor
manufacture’s data sheet should be consulted to ensure
the desired capacitance at all temperatures and voltages.
Table 1 is a list of ceramic capacitor manufacturers and
their websites.
Table 1
AVX www.avxcorp.com
Kemet www.kemet.com
Murata www.murata.com
Taiyo Yuden www.t-yuden.com
Vishay www.vishay.com
TDK www.component.tdk.com
Layout Considerations
Due to high switching frequency and high transient currents
produced by LTC3260, careful board layout is necessary
for optimum performance. A true ground plane and short
connections to all the external capacitors will improve
performance and ensure proper regulation under all condi-
tions. Figure 5 shows an example layout for the LTC3260.
The flying capacitor nodes C
+
and C
switch large cur-
rents at a high frequency. These nodes should not be
routed close to sensitive pins such as the LDO feedback
pins (ADJ
+
and ADJ
) and internal reference bypass pins
(BYP
+
and BYP
).
Thermal Management
At high input voltages and maximum output current, there
can be substantial power dissipation in the LTC3260. If
the junction temperature increases above approximately
175°C, the thermal shutdown circuitry will automatically
deactivate the output. To reduce the maximum junction
temperature, a good thermal connection to the PC board
ground plane is recommended. Connecting the exposed pad
of the package to a ground plane under the device on two
layers of the PC board can reduce the thermal
resistance
of the package and PC board considerably.
Derating Power at High T
emperatures
To prevent an overtemperature condition in high power
applications, Figure 6 should be used to determine the
maximum combination of ambient temperature and power
dissipation.
The power dissipated in the LTC3260 should always fall
under the line shown for a given ambient temperature. The
power dissipated in the LTC3260 has three components.
Power dissipated in the positive LDO:
P
LDO
+
= (V
IN
– V
LDO
+
) • I
LDO
+
Power dissipated in the negative LDO:
P
LDO
= (|V
OUT
| – |V
LDO
|) • I
LDO
and
Power dissipated in the inverting charge pump:
P
CP
= (V
IN
– |V
OUT
|) • (I
OUT
+ I
LDO
)
where I
OUT
denotes any additional current that might be
pulled directly from the V
OUT
pin. The LDO
current is
also supplied by the charge pump through V
OUT
and is
therefore included in the charge pump power dissipation.
The total power dissipation of the LTC3260 is given by:
P
D
= P
LDO
+
+ P
LDO
+ P
CP
Figure 5. Recommended Layout
V
OUT
V
IN
LDO
LDO
+
GND
3260 F05
C
BYP
+
C
F LY
GND
RT
C
BYP

LTC3260IMSE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Controllers Low Noise Dual Supply Inverting Charge Pump
Lifecycle:
New from this manufacturer.
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