LTC3260
7
3260fa
pin FuncTions
(DFN/MSOP)
EN
+
(Pin 1/ Pin 1): Logic Input. A logichigh” on the EN
+
pin enables the positive low dropout (LDO
+
) regulator.
RT (Pin 2/Pin 2): Input Connection for Programming the
Switching Frequency. The RT pin servos to a fixed 1.2V
when the EN
pin is driven to a logichigh”. A resistor from
RT to GND sets the charge pump switching frequency. If
the RT pin is tied to GND, the switching frequency defaults
to a fixed 500kHz.
BYP
(Pin 3/ Pin 3): LDO
Reference Bypass Pin. Connect
a capacitor from BYP
to GND to reduce LDO
output
noise. Leave floating if unused.
ADJ
(Pin 4/ Pin 4): Feedback Input for the Negative Low
Dropout Regulator. This pin servos to a fixed voltage of
–1.2V when the control loop is complete.
LDO
(Pin 5/ Pin 5): Negative Low Dropout (LDO
) Linear
Regulator Output. This pin requires a low ESR (equivalent
series resistance) capacitor with at leastF capacitance
to ground for stability.
V
OUT
(Pin 6/ Pin 6): Charge Pump Output Voltage. In
constant frequency mode (MODE = low) this pin is driven
toV
IN
. In Burst Mode operation, (MODE = high) this pin
voltage is regulated to –0.94 V
IN
using an internal burst
comparator with hysteretic control.
C
(Pin 7/ Pin 7): Flying Capacitor Negative Connection.
C
+
(Pin 8/ Pin 10): Flying Capacitor Positive Connection.
NC (Pins 8, 9 MSOP Only): No Connect. These pins are not
connected to the LT C 3260 die. These pins should be left
floating, connected to ground or shorted to adjacent pins.
V
IN
(Pin 9/ Pin 11): Input Voltage for Both Charge Pump
and Positive Low Dropout (LDO
+
) Regulator. V
IN
should
be bypassed with a low impedance ceramic capacitor.
LDO
+
(Pin 10/ Pin 12): Positive Low Dropout (LDO
+
)
Output. This pin requires a low ESR capacitor with at least
2µF capacitance to ground for stability.
EN
(Pin 11/ Pin 13): Logic Input. A logichigh” on the
EN
pin enables the inverting charge pump as well as the
negative LDO regulator.
MODE (Pin 12/ Pin 14): Logic Input. The MODE pin deter-
mines the charge pump operating mode. A logichigh”
on the MODE pin forces the charge pump to operate in
Burst Mode operation regulating V
OUT
to approximately
–0.94 V
IN
with hysteretic control. A logiclow” on the
MODE pin forces the charge pump to operate as an open-
loop inverter with a constant switching frequency. The
switching
frequency in both modes is determined by an
external resistor from the RT pin to GND. In Burst Mode
operation, this represents the frequency of the burst cycles
before the part enters the low quiescent current sleep state.
ADJ
+
(Pin 13/ Pin 15): Feedback Input for the Positive
Low Dropout (LDO
+
) Regulator. This pin servos to a fixed
voltage of 1.2V when the control loop is complete.
BYP
+
(Pin 14/Pin 16): LDO
+
Reference Bypass Pin. Con-
nect a capacitor from BYP
+
to GND to reduce LDO
+
output
noise. Leave floating if unused.
GND (Exposed Pad Pin 15/ Exposed Pad Pin 17): Ground.
The exposed package pad is ground and must be soldered
to the PC board ground plane for proper functionality and
for rated thermal performance.
LTC3260
8
3260fa
block DiagraM
Note: Pin numbers are as per DFN package. Refer to the Pin Functions section for corresponding MSOP pin numbers.
9 10
13
14
+
+
1.2V
REF
INVERTING
CHARGE PUMP
–1.2V
REF
CHARGE
PUMP
AND
INPUT
LOGIC
50kHz
TO
500kHz
OSC
LDO
+
EN
+
V
IN
C
+
S1
S4
S3
ADJ
+
BYP
+
3
4
BYP
ADJ
5
15
LDO
GND
1
8
C
S2
7
RT
2
EN
11
MODE
12
V
OUT
6
operaTion
(Refer to the Block Diagram)
The LTC3260 is a high voltage low noise dual output
regulator. It includes an inverting charge pump and two
LDO regulators to generate bipolar low noise supply rails
from a single positive input. It supports a wide input power
supply range from 4.5V to 32V.
Shutdown Mode
In shutdown mode, all circuitry except the internal bias is
turned off. The LTC3260 is in shutdown when a logic low
is applied to both the enable inputs (EN
+
and EN
). The
LTC3260 only drawsA (typical) from the V
IN
supply
in shutdown.
Charge Pump Constant Frequency Operation
The LTC3260 provides low noise constant frequency op-
eration when a logic low is applied to the MODE pin. The
charge pump and oscillator circuit are enabled using the
EN
pin. At the beginning of a clock cycle, switches S1 and
S2 are closed. The external flying capacitor across the C
+
and C
pins is charged to the V
IN
supply. In the second
phase of the clock cycle, switches S1 and S2 are opened,
while switches S3 and S4 are closed. In this configuration
the C
+
side of the flying capacitor is grounded and charge
is delivered through the C
pin to V
OUT
. In steady state
the V
OUT
pin regulates atV
IN
less any voltage drop due
to the load current on V
OUT
or LDO.
LTC3260
9
3260fa
operaTion
(Refer to the Block Diagram)
Figure 1. Oscillator Frequency vs R
T
The charge transfer frequency can be adjusted between
50kHz and 500kHz using an external resistor on the RT
pin. At slower frequencies the effective open-loop output
resistance (R
OL
) of the charge pump is larger and it is able
to provide smaller average output current. Figure 1 can
be used to determine a suitable value of RT to achieve a
required oscillator frequency. If the RT pin is grounded,
the part operates at a constant frequency of 500kHz.
R
T
(kΩ)
200
OSCILLATOR FREQUENCY (kHz)
400
600
100
300
500
1 100 1000 10000
3260 F01
0
10
Charge Pump Burst Mode Operation
The LTC3260 provides low power Burst Mode operation
when a logic high is applied to the MODE pin. In Burst
Mode operation, the charge pump charges the V
OUT
pin to
–0.94 V
IN
(typical). The part then shuts down the internal
oscillator to reduce switching losses and goes into a low
current state. This state is referred to as the sleep state in
which the IC consumes only about 100µA with both LDOs
enabled. When the output voltage droops enough to over-
come the burst comparator hysteresis, the part wakes up
and commences charge pump cycles until output voltage
exceeds –0.94 V
IN
(typical). This mode provides lower
operating current at the cost of higher output ripple and
is ideal for light load operation.
The frequency of charging cycles is set by the external
resistor on the RT pin. The charge pump has a lower
R
OL
at higher frequencies. For Burst Mode operation it is
recommended that the RT pin be tied to GND. This mini-
mizes the charge pump R
OL
, quickly charges the output
up to the burst threshold and optimizes the duration of
the low current sleep state.
Charge Pump Soft-Start
The LTC
3260 has built in soft-start circuitry to prevent
excessive
current flow during start-up. The soft-start is
achieved by internal circuitry that slowly ramps the amount
of current available at the output storage capacitor. The
soft-start circuitry is reset in the event of a commanded
shutdown or thermal shutdown.
Charge Pump Short-Circuit/Thermal Protection
The LTC3260 has built-in short-circuit current limit as
well as overtemperature protection. During a short-circuit
condition, the part automatically limits its output current
to approximately 160mA. If the junction temperature
exceeds approximately 175°C the thermal shutdown
circuitry disables current delivery to the output. Once
the junction temperature drops back to approximately
165°C current delivery to the output is resumed. When
thermal protection is active the junction temperature is
beyond the specified operating range. Thermal protection
is intended for momentary overload conditions outside
normal operation. Continuous operation above the speci-
fied maximum operating junction temperature may impair
device reliability.
Positive Low Dropout Linear Regulator (LDO
+
)
The positive low dropout regulator (LDO
+
) supports a load
of up to 50mA. The LDO
+
takes power from the V
IN
pin
and drives the LDO
+
output pin to a voltage programmed
by the resistor divider connected between the LDO
+
, ADJ
+
and GND pins. For stability, the LDO
+
output must be by-
passed to ground with a low ESR ceramic capacitor that
maintains a capacitance of at leastF across operating
temperature and voltage.
The LDO
+
is enabled or disabled via the EN
+
logic input pin.
When the LDO
+
is enabled, a soft-start circuit ramps its
regulation point from zero to the final value over a period
of 75µs, reducing the inrush current on V
IN
.

LTC3260IMSE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Controllers Low Noise Dual Supply Inverting Charge Pump
Lifecycle:
New from this manufacturer.
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