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1. General description
The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC00 and 74HCT00.
The 74LV00 provides a quad 2-input NAND function.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25 C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25 C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
3. Ordering information
74LV00
Quad 2-input NAND gate
Rev. 4 — 9 December 2015 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV00D 40 Cto+125C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LV00DB 40 Cto+125C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LV00PW 40 Cto+125C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LV00BQ 40 Cto+125C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
SOT762-1
74LV00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 9 December 2015 2 of 14
NXP Semiconductors
74LV00
Quad 2-input NAND gate
4. Functional diagram
5. Pinning information
5.1 Pinning
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
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(1) This is not a supply pin. The substrate is attached to this
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CC
.
Fig 4. Pin configuration SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14
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74LV00PW/AUJ

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Logic Gates Quad 2-input NAND gate
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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