74LV00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 9 December 2015 6 of 14
NXP Semiconductors
74LV00
Quad 2-input NAND gate
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. The input (nA, nB) to output (nY) propagation delays
DDK
W
3+/
W
3/+
9
0
9
0
Q<RXWSXW
Q$Q%LQSXW
9
,
*1'
9
2+
9
2/
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
M
V
M
< 2.7 V 0.5V
CC
0.5V
CC
2.7 V to 3.6 V 1.5 V 1.5 V
4.5 V 0.5V
CC
0.5V
CC
Test data is given in Table 9.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
Fig 7. Test circuit for measuring switching times
9
&&
9
,
9
2
DDD
'87
&
/
S)
5
7
5
/
Nȍ
38/6(
*(1(5$725
Table 9. Test data
Supply voltage Input
V
CC
V
I
t
r
, t
f
< 2.7 V V
CC
2.5 ns
2.7 V to 3.6 V 2.7 V 2.5 ns
4.5 V V
CC
2.5 ns
