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HCPL-315J-500E

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
16
The value of 4.25 mA for I
CC
in the previous equation was
obtained by derating the I
CC
max of 5 mA (which occurs
at -40°C) to I
CC
max at 90°C (see Figure 7).
Since P
O
for this case is greater than P
O(MAX)
, Rg must be
increased to reduce the HCPL-3150 power dissipation.
P
O(SWITCHING MAX)
= P
O(MAX)
- P
O(BIAS)
= 154 mW - 85 mW
= 69 mW
P
O(SWITCHINGMAX)
E
SW(MAX)
=
f
69 mW
= = 3.45 µJ
20 kHz
For Qg = 500 nC, from Figure 27, a value of E
SW
= 3.45 µJ
gives a Rg = 41 Ω.
Thermal Model (HCPL-3150)
The steady state thermal model for the HCPL-3150 is
shown in Figure 28a. The thermal resistance values given
in this model can be used to calculate the tempera tures
at each node for a given operating condition. As shown
by the model, all heat generated ows through θ
CA
which
raises the case temperature T
C
accordingly. The value of
θ
CA
depends on the conditions of the board design and
is, therefore, determined by the designer. The value of
θ
CA
= 83°C/W was obtained from thermal measure-
ments using a 2.5 x 2.5 inch PC board, with small traces
(no ground plane), a single HCPL-3150 soldered into
the center of the board and still air. The absolute maxi-
mum power dissipation derating specica tions assume
a θ
CA
value of 83°C/W.
From the thermal mode in Figure 28a the LED and detec-
tor IC junction temperatures can be expressed as:
T
JE
= P
E
•
(θ
LC
||(θ
LD
+ θ
DC
) + θ
CA
)
θ
LC
•
θ
DC
+ P
D
•
( + θ
CA
) + T
A
θ
LC
+ θ
DC
+ θ
LD
θ
LC
•
θ
DC
T
JD
=
P
E
( + θ
CA
)
θ
LC
+ θ
DC
+ θ
LD
+ P
D
•
(θ
DC
||(θ
LD
+ θ
LC
) + θ
CA
) + T
A
Inserting the values for θ
LC
and θ
DC
shown in Figure 28
gives:
T
JE
= P
E
•
(230°C/W + θ
CA
) + P
D
•
(49°C/W + θ
CA
) + T
A
T
JD
= P
E
•
(49°C/W + θ
CA
) + P
D
•
(104°C/W + θ
CA
) + T
A
For example, given P
E
= 45 mW, P
O
= 250 mW, T
A
= 70°C
and θ
CA
= 83°C/W:
T
JE
= P
E
•
313°C/W + P
D
•
132°C/W + T
A
= 45 mW
•
313°C/W + 250 mW
•
132°C/W + 70°C = 117°C
T
JD
= P
E
•
132°C/W + P
D
•
187°C/W + T
A
= 45 mW
•
132C/W + 250 mW
•
187°C/W + 70°C = 123°C
T
JE
and T
JD
should be limited to 125°C based on the board
layout and part placement (θ
CA
) specic to the applica-
tion.
T
JE
= LED junction temperature
T
JD
= detector IC junction temperature
T
C
= case temperature measured at the center of the package bottom
θ
LC
= LED-to-case thermal resistance
θ
LD
= LED-to-detector thermal resistance
θ
DC
= detector-to-case thermal resistance
θ
CA
= case-to-ambient thermal resistance
∗θ
CA
will depend on the board design and the placement of the part.
Figure 28a. Thermal Model.
HCPL-3150 fig 28
θ
LD
= 439°C/W
T
JE
T
JD
θ
LC
= 391°C/W θ
DC
= 119°C/W
θ
CA
= 83°C/W*
T
C
T
A
T
JE
= LED JUNCTION TEMPERATURE
T
JD
= DETECTOR IC JUNCTION TEMPERATURE
T
C
= CASE TEMPERATURE MEASURED AT THE
CENTER OF THE PACKAGE BOTTOM
θ
LC
= LED-TO-CASE THERMAL RESISTANCE
θ
LD
= LED-TO-DETECTOR THERMAL RESISTANCE
θ
DC
= DETECTOR-TO-CASE THERMAL RESISTANCE
θ
CA
= CASE-TO-AMBIENT THERMAL RESISTANCE
*
θ
CA
WILL DEPEND ON THE BOARD DESIGN AND
THE PLACEMENT OF THE PART.
17
Thermal Coecient Data (units in °C/W)
Part Number A
11
, A
22
A
12
, A
21
A
13
, A
31
A
24
, A
42
A
14
, A
41
A
23
, A
32
A
33
, A
44
A
34
, A
43
HCPL-315J 198 64 62 64 83 90 137 69
Note: Maximum junction temperature for above part: 125°C.
Figure 28b. Thermal Impedance Model for HCPL-315J.
θ
6
θ
5
θ
9
θ
4
θ
8
θ
7
θ
10
θ
1
θ
3
θ
2
LED 1 LED 2
AMBIENT
DETECTOR 1 DETECTOR 2
HCPL-3150 fig 28b
P
E1
HCPL-3150 fig 28b
P
E2
P
D1
P
D2
Thermal Model Dual-Channel (SOIC-16) HCPL-315J Op-
toisolator
Denitions
θ
1
, θ
2
, θ
3
, θ
4
, θ
5
, θ
6
, θ
7
, θ
8
, θ
9
, θ
10
: Thermal impedances be-
tween nodes as shown in Figure 28b. Ambient Tempera-
ture: Measured approximately 1.25 cm above the opto-
coupler with no forced air.
Description
This thermal model assumes that a 16-pin dual-channel
(SOIC-16) optocoupler is soldered into an 8.5 cm x 8.1
cm printed circuit board (PCB). These optocouplers are
hybrid devices with four die: two LEDs and two detec-
tors. The temperature at the LED and the detector of the
optocoupler can be calculated by using the equations
below.
∆T
E1A
= A
11
P
E1
+ A
12
P
E2
+A
13
P
D1
+A
14
P
D2
∆T
E2A
= A
21
P
E1
+ A
22
P
E2
+A
23
P
D1
+A
24
P
D2
∆T
D1A
= A
31
P
E1
+ A
32
P
E2
+A
33
P
D1
+A
34
P
D2
∆T
D2A
= A
41
P
E1
+ A
42
P
E2
+A
43
P
D1
+A
44
P
D2
where:
∆T
E1A
= Temperature dierence between ambient and LED 1
∆T
E2A
= Temperature dierence between ambient and LED 2
∆T
D1A
= Temperature dierence between ambient and detector 1
∆T
D2A
= Temperature dierence between ambient and detector 2
P
E1
= Power dissipation from LED 1;
P
E2
= Power dissipation from LED 2;
P
D1
= Power dissipation from detector 1;
P
D2
= Power dissipation from detector 2
A
xy
thermal coecient (units in °C/W) is a function of thermal imped-
ances θ
1
through θ
10
.
18
CMR with the LED On (CMR
H
)
A high CMR LED drive circuit must keep the LED on dur-
ing common mode transients. This is achieved by over-
driving the LED current beyond the input threshold so
that it is not pulled below the threshold during a tran-
sient. A minimum LED cur rent of 10 mA provides ade-
quate margin over the maximum I
FLH
of 5 mA to achieve
15 kV/µs CMR.
Figure 27. Energy Dissipated in the HCPL-3150
for Each IGBT Switching Cycle.
Esw – ENERGY PER SWITCHING CYCLE – µJ
0
0
Rg – GATE RESISTANCE – Ω
100
3
20
HCPL-3150 fig 27
7
40
2
60 80
6
Qg = 100 nC
Qg = 250 nC
Qg = 500 nC
5
4
1
V
CC
= 19 V
V
EE
= -9 V
LED Drive Circuit Considerations for Ultra High CMR Per-
formance
Without a detector shield, the dominant cause of opto-
coupler CMR failure is capacitive coupling from the in-
put side of the optocoupler, through the package, to the
detector IC as shown in Figure 29. The HCPL-3150/315J
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts
the capaci tively coupled current away from the sensitive
IC circuitry. How ever, this shield does not eliminate the
capacitive coupling between the LED and optocoup ler
pins 5-8 as shown in Figure 30. This capacitive coupling
causes perturbations in the LED current during common
mode transients and becomes the major source of CMR
failures for a shielded optocoupler. The main design ob-
jective of a high CMR LED drive circuit becomes keeping
the LED in the proper state (on or o) during common
mode transients. For example, the recommended ap-
plication circuit (Figure 25), can achieve 15 kV/µs CMR
while minimizing component complexity.
Techniques to keep the LED in the proper state are dis-
cussed in the next two sections.
CMR with the LED O (CMR
L
)
A high CMR LED drive circuit must keep the LED o
(V
F
≤ V
F(OFF)
) during common mode transients. For exam-
ple, during a -dV
CM
/dt transient in Figure 31, the current
owing through C
LEDP
also ows through the R
SAT
and V
SAT
of the logic gate. As long as the low state voltage devel-
oped across the logic gate is less than V
F(OFF)
, the LED will
remain o and no common mode failure will occur.
The open collector drive circuit, shown in Figure 32, can-
not keep the LED o during a +dV
CM
/dt transient, since
all the current owing through C
LEDN
must be supplied
by the LED, and it is not recommended for applications
requiring ultra high CMR
L
performance. Figure 33 is an
alternative drive circuit which, like the recommended
application circuit (Figure 25), does achieve ultra high
CMR performance by shunting the LED in the o state.
Under Voltage Lockout Feature
The HCPL-3150/315J contains an under voltage lockout
(UVLO) feature that is designed to protect the IGBT under
fault conditions which cause the HCPL-3150/315J supply
voltage (equivalent to the fully-charged IGBT gate volt-
age) to drop below a level necessary to keep the IGBT in
a low resistance state. When the HCPL-3150/315J output
is in the high state and the supply voltage drops below
the HCPL-3150/315J V
UVLO-
threshold (9.5 <V
UVLO-
<12.0),
the optocoupler output will go into the low state with
a typical delay, UVLO Turn O Delay, of 0.6 µs. When the
HCPL-3150/315J output is in the low state and the supply
voltage rises above the HCPL-3150/315J V
UVLO+
threshold
(11.0 < V
UVLO+
< 13.5), the optocoupler will go into the high
state (assuming LED is “ON”) with a typical delay, UVLO
TURN On Delay, of 0.8 µs.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

HCPL-315J-500E

Mfr. #:
Buy HCPL-315J-500E
Manufacturer:
Broadcom / Avago
Description:
Logic Output Optocouplers 0.5A IGBT Gate Drive
Lifecycle:
New from this manufacturer.
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