XRD9818ACG Datasheet XRD9818ACGTR-F, XRD9818ACG, XRD9818ACG-F | P10-P12

XRD9818 xrxr

3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR

REV. 1.0.1

2.4 3-CH CIS Mode

In this mode the XRD9818 simultaneously samples (S/H) the red, green and blue channel inputs. The video

level is sampled on the falling edge of VSAMP. Each channels S/H extracts the video information from each

pixel. This data is level shifted and gained up according to the contents of the Offset and PGA registers

respectively. The data is then sequentially converted (Red

→ Green → Blue) by a 16-bit A/D converter.

In CIS mode, each channel input is sampled with respect to the voltage at the CMN- input. The voltage at

CMN- can be either generated by a programmable internal reference (C/R DAC) or supplied by an external

source.

The timing for this mode is shown in Figure18.

2.5 2-CH CIS Mode

The 2-CH mode operates identically to the 3-CH CIS mode except that only 2 channels are actively used to

process CIS output signals. The two channels to be used and the order in which they process data is

determined from the configuration of the Input-Mux/Channel-Select bits (CH[2:0]) located in the Mode 1

not being utilized is powered down.

2.6 1-CH CIS Mode

The 1-CH mode operates identically to the 3-CH or 2-CH CIS modes except that the channel sampled is fixed

to only one input. The channel selection is set by the Input-Mux/Channel-Select bits (CH[2:0]) located in the

Mode 1 register. There are three possible one channel modes: R, G or B. The channels not being used will be

powered down.

xrxr XRD9818

3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR

REV. 1.0.1

3.0 REGISTER MAP

Note: * Exar test bits, do not over write the default values.

Shaded cells represent unused bits.

3.1 PGA Gain Registers

There are three PGA registers for individually programming the gain in the RED, GREEN, and BLUE channels.

Each gain register has 9 bits of resolution. Bits D[9:1] control the gain while bit D0 is N/A (don’t care). The

XRD9818 has two gain ranges to help interface to imagers that have 3V or 2V of output signal swing. The GS

bit, located in the MODE 1 register, defaults to GS=0 for a gain of 1x to 5x or if GS=1 the gain would be 1.5x to

7.5x. The gain range of 1 to 5x (GS=0) is intended for use with imagers that have a 3V output swing, while the

gain range 1.5 to 7.5x is intended for imagers with 2V or less of output swing. The coding for the PGA registers

is straight binary. See “Section 4.3, Programmable Gain” on page20 for a functional description of the

XRD9818’s gain stage.

* Power-on default value

INTERNAL REGISTER MAP

Name

Address Data Bits

A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

RED Gain 0 0 0 0 msb lsb

GREEN Gain 0 0 0 1 msb lsb

BLUE Gain 0 0 1 0 msb lsb

RED Offset 0 0 1 1 COR[1] COR[0] FOR[7] FOR[6] FOR[5] FOR[4] FOR[3] FOR[2] FOR[1] FOR[0]

GREEN Offset 0 1 0 0 COG[1] COG[0] FOG[7] FOG[6] FOG[5] FOG[4] FOG[3] FOG[2] FOG[1] FOG[0]

BLUE Offset 0 1 0 1 COB[1] COB[0] FOB[7] FOB[6] FOB[5] FOB[4] FOB[3] FOB[2] FOB[1] FOB[0]

MODE 1 0 1 1 0 CH[2] CH[1] CH[0] GS LC CCD

B/N C/R[2] C/R[1] C/R[0]

MODE 2 0 1 1 1 PD OE

pol

ADC

pol

BSAMP

Delay

1 0 0 0 BL[4] BL[3] BL[2] BL[1] BL[0] BT[4] BT[3] BT[2] BT[1] BT[0]

VSAMP

Delay

1 0 0 1 VL[4] VL[3] VL[2] VL[1] VL[0] VT[4] VT[3] VT[2] VT[1] VT[0]

ADCLK

Delay

1 0 1 0 A[4] A[3] A[2] A[1] A[0] DO[4] DO[3] DO[2] DO[1] DO[0]

TEST 1 0 1 1 * * * * * * * * * *

RESET/RB 1 1 1 1 Reset READ RB[3] RB[2] RB[1] RB[0]

GAIN REGISTER SETTINGS

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (V/V) Gain (V/V)

msb lsb N/A w/GS bit = 0* w/GS bit = 1

000000000*

…

111111111

not

used

…

1.5x

…

7.5x

XRD9818 xrxr

3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR

REV. 1.0.1

3.2 Offset Registers

There are three Offset registers for individual control of the offsets applied to the RED, GREEN, and BLUE

channels. There are separate course and fine controls to set the desired offset compensation for each channel.

Bits D9 and D8 set the course offset from -100mV to +200mV in 100mV increments. Bits D7:D0 set the fine

offset range from -180mV to +180mV in 1.4mV increments. The polarity of the offset correction is defined as

positive for the normal direction in which offsets occur in an imager, see Figure11. Please see “Section 4.2,

Programmable Offset Adjust” on page19 for a description of the XRD9818’s offset correction circuitry.

* Power-on default value

3.3 Mode Registers

There are two mode registers that control the configuration and operation of the XRD9818. The Mode 1

or nibble data output mode and clamp level select. The Mode 2 register controls the power down, output

enable and polarities of the input timing signals.

* Power-on default value

CH[2:0] - Input Mux/Channel select. Selects between 3-CH (RGB), 1-CH RED, 1-CH GRN,

1-CH BLU, 2-CH (RG), 2-CH (GR), 2-CH (GB) or 2-CH (BR) input mux modes.

GS - Gain Range Select. Gain range 1x to 5x for 3V input signals, range 1.5x to 7.5x for 2V signals.

LC- Line Clamp enable. Gates clamping function with the timing signal LCLMP.

CCD

- CCD enable. Defines operation for a CCD or CIS imager input.

B/N - Byte or Nibble output mode. Defines 8bit (byte) or 4bit (nibble) data output format.

C/R[2:0] - Clamp/Reference Select. The setting determines the clamp/reference voltage applied

to the CMN- input. The settings 2.0V through VDD are intended for use in CCD applications.

The 0V, 1.25V or "high Z" settings are intended for use for CIS applications. If "high Z"

is selected an external source can be applied to CMN- for the reference. For a description

of the C/R DAC please See “Section 4.1.2, Clamp/Reference (C/R) DAC” on page17.

OFFSET REGISTER SETTINGS

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

COx[1] COx[0] FOx[7] FOx[6] FOx[5] FOx[4] FOx[3] FOx[2] FOx[1] FOx[0]

Course offset

control

00*

→ 0mV

→ -100mV

→ 100mV

→ 200mV

Fine offset control

01111111

→ 150mV

…

00000000*

→ 0mV

10000000

→ 0mV

…

11111111

→ -150mV

MODE 1 REGISTER SETTINGS

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CH[2] CH[1] CH[0] GS LC CCD

B/N C/R[2] C/R[1] C/R[0]

000* → 3CH (RGB)

001

→ RED channel

010

→ GRN channel

011

→ BLU channel

100

→ 2CH (RG)

101

→ 2CH (GR)

110

→ 2CH (GB)

111

→ 2CH (BR)

→ 1x to 5x

→ 1.5x to 7.5x

→ Line Clamp

Off

→ Line Clamp

→ CCD

→ CIS

→ byte output

mode

→ nibble out-

put mode

000

→ high Z

001

→ 0V

010

→ 1.25V

011

→ 2.0V

100

→ 2.6V

101

→ 2.8V

110*

→3.0V

111 → VDD

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

XRD9818ACG

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XRD9818ACG

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