XRD9818 xrxr
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
4.0 CIRCUIT OPERATION
4.1 Analog Inputs
4.1.1 Sampling
The XRD9818’s analog front end (AFE) uses a switched capacitor network to achieve a correlated double
sample (CDS) of the input in CCD mode or a sample and hold (S/H) of the input in CIS mode. Figure3 shows
the 9818’s AFE (CDS/SH + PGA) which samples and gains the input signal. Figure4 shows the external and
internal timing requirements to achieve a correlated double sample and gain of a CCD input signal.
In addition to sampling and gaining the CCD signal the 9818 input is designed to reject the reset pulse noise
present also. The XRD9818 can withstand reset pulses up to 1.5V or more depending upon the input
conditions. The timing signal
φ
R
controls SW2 and SW3 is generated internally by the XRD9818. SW2 and
SW3 open after a short delay following the sampling edge of VSAMP and close at the leading edge of BSAMP.
The XRD9818 utilizes a differential input and signal path which samples the CCD reference level on capacitors
C1 and C2. When
φ
B
goes high, SW4 and SW5 close storing the CCD reference level on C1 and C2. When
φ
B
goes low a fixed gain is applied to the input signal as it tracks the video input. When φ
V
goes high the video
content is applied to capacitors C5 and C6. The final video level is stored on C5 and C6 when
φ
V
goes low.
The video content is then amplified again and sampled by the ADC at the proper time
F
IGURE 3. XRD9818 INPUT CIRCUITRY
FIGURE 4. INTERNAL AFE SAMPLE TIMING (EX. 3CH CCD MODE)
φ
B
φ
B
φ
V
φ
V
φ
V
φ
V
φ
R
to ADC
φ
CL
C1
C2
C3
C4
C5
C6
C7
C8
C1 = C2 = 7.5pf
C3 = C4 = 7.5pf or 11pf
C5 = C6 = 1.5pf or 7.89pf
C7 = C8 = 1pf
SW1
SW2
SW3
SW4
φ
R
SW5
SW6
SW7
SW8
SW9
Input
Reference
CCD
IN
ADCLK
byte
BSAMP
VSAMP
ADCLK
nibble
φ
R
φ
B
φ
V
φ
Note :
