XRD9818ACG Datasheet XRD9818ACGTR-F, XRD9818ACG, XRD9818ACG-F | P19-P21

xrxr XRD9818

3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR

REV. 1.0.1

4.2 Programmable Offset Adjust

The offset adjustment circuitry of the XRD9818 is designed to compensate for any offsets present in the CCD

or CIS output signal and/or overall scanner system. The total range of compensation available is -280mV to

+380mV. This is achieved via a 10-bit Offset DAC that applies gain independent offset correction. The 10-bits

of control is broken into 2 ranges, course and fine. There are 2 bits of course control that is designed to

remove offsets in 100mV increments. The remaining 8-bits determine the fine control and has a range of

+/-180mV in 1.4mV increments. Each channel has its own independent offset control.

The offset correction range of both the Course and Fine DAC’s are shown in Figure10. The Course DAC has

four settings: 0mv, -100mV, 100mV and 200mV. The 2 msb’s, D[9:8], select the desired course offset setting.

The Fine DAC has a range of +/-180mV. The Offset registers 8 lsb’s, D[7:0], select the desired fine setting.

Bits D[6:0] program the magnitude while D[7] selects the polarity of the Fine DAC’s compensation.

As can be seen in the Course Offset DAC’s range settings there is more correction range in the positive

direction. This allows the system designer to maximize the usable offset correction range of the XRD9818 for a

variety of imagers. Positive offset is defined as the normal offset direction found in either a CCD or CIS input

signal, as shown in Figure11.

IGURE 9. XRD9818 CHANNEL OFFSET BLOCK DIAGRAM

FIGURE 10. OFFSET CORRECTION (COURSE & FINE DAC’S)

IGURE 11. SIGNAL OFFSET POLARITY (CCD AND CIS)

CDS

Input

ADC

16-Bit

3:1

MUX

8-Bit2-Bit

Programmable Serial Port

8-Bit Offset DAC

Fine Adjust

2-Bit Offset

Course Adjust

Offset Block

PGA

9-Bit

Code

Fine DAC

Range

150mV

-150mV

00h 0Fh

10h

FFh

Course DAC Settings

COx[1:0] Offset (mV)

-100

100

200

Negative Offset

Positive Offset

Ideal Black

White

Signal

CCD Dark Offset

Negative Offset

Positive Offset

Ideal Black

White

Signal

CCD CIS

XRD9818 xrxr

3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR

REV. 1.0.1

The affect of the XRD9818’s offset correction DAC’s (Course & Fine) is defined as follows:

The course DAC value, VOS

COURSE

, is defined in Figure10 and the Fine DAC value is determined as follows:

The XRD9818 offset adjustment range is designed to maximize the correction range whether being used in a

CCD or CIS application.

4.3 Programmable Gain

There are three independent PGA’s, one for each input channel: Red, Green and Blue. The individual gain

values are controlled by separate Red, Green and Blue gain registers. Each PGA has 9 bits of control for the

full gain range. See Figure12 for the PGA transfer function. The gain increments in a binary fashion from a

minimum at code 0 to a maximum at code 511.

The PGA has two gain ranges 1x to 5x and 1.5x to 7.5x to help interface to imagers with 3V or 2V outputs

respectively. To select the 1x to 5x gain range for an imager that has a 3V single swing the GS bit in the

MODE 1 register must be set low, GS=0 (default). To select the 1.5x to 7.5x gain range for use with imagers

that have a 2V maximum signal swing the GS bit in the MODE 1 register must be set high, GS=1.

The XRD9818 channel gain equations are as follows:

IGURE 12. XRD9818 PGA TRANSFER FUNCTION

= V

Input

- (VOS

Course

+ VOS

Fine

) note: positive offset values subtract from the input signal

VOS

Fine

(

)

FBx[7]

Offset Code

127

150mV













FBx[6:0]

Note : FB[7] = 0 -> (+), FB[7] = 1 -> (-)

0 64 128 192 256 320 384 448 512

PGA Gain Code

Gain (V/V)

GS=1

GS=0

Gain

1 to 5

Gain Code

511

4 1

Gain

1.5 to 7.5

Gain Code

511

6.0 1.5or

xrxr XRD9818

3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR

REV. 1.0.1

5.0 SERIAL PORT INTERFACE

The XRD9818 can be configured through a three pin interface (LOAD, SDI, and SCLK) with the serial port write

timing shown below. Each write will include 4 bits of address, two dummy bits and 10 bits of data. To insure

a valid write operation, the serial port control must detect minimum of 16 rising SCLK edges. Upon a valid

write the XRD9818 will latch the last 16 bits of data presented at the rising edge of LOAD. The register

address will be decoded and the 10bits of data will over write the contents of the addressed register. The

LOAD setup time "Tls" can be indefinitely long.

LOAD is used to gate the SCLK input into the XRD9818. In order to eliminate any unintended high speed

clocks into the part it is recommended that the LOAD signal only be active during the write operation.

IGURE 13. SERIAL PORT WRITE TIMING

FIGURE 14. LOAD GATING OF SCLK

A3 A2 A1

D7 D6 D5 D4 D3 D2 D1 D0D8D9

msb msblsb lsb

LOAD

SCLK

SDI

Tsclk

Tds

Tls

Tlh

Write Register Data

Tdh

Tlpw

SCLK

LOAD

SCLK

(internal)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

XRD9818ACG

Mfr. #:

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MaxLinear

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IC AFE 3 CHAN 16BIT 28TSSOP

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XRD9818ACG

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