OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

TDF8590TH/N1TJ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
TDF8590TH_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 23 April 2007 10 of 30
NXP Semiconductors
TDF8590TH
2 × 80 W SE (4 Ω) or 1 × 160 W BTL (8 Ω) class-D amplifier
7. Limiting values
Input resistors are referred to SGND.
a. Internal circuitry
b. External connections
Fig 8. Input configuration for mono BTL application
001aad841
IN1P
SGND
IN1M
IN2P
IN2M
V
in
IN1P
OUT1
power stage
mbl466
OUT2
SGND
IN1M
IN2P
IN2M
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage V
DDP1
and V
DDA1
referred to
SGND1; V
DDP2
and V
DDA2
referred
to SGND2
−0.3 +34 V
V
SS
negative supply voltage V
SSP1
and V
SSA1
referred to
SGND1; V
SSP2
and V
SSA2
referred
to SGND2
−34 +0.3 V
V
P
supply voltage −0.3 +66 V
I
OSM
non-repetitive peak output current - 12 A
T
stg
storage temperature −55 +150 °C
T
amb
ambient temperature −40 +85 °C
T
j
junction temperature −40 +150 °C
V
BOOT1
voltage on pin BOOT1 referred to OUT1
[1]
014V
V
BOOT2
voltage on pin BOOT2 referred to OUT2
[1]
014V
V
STABI
voltage on pin STABI referred to V
SSD
[2]
-14V
TDF8590TH_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 23 April 2007 11 of 30
NXP Semiconductors
TDF8590TH
2 × 80 W SE (4 Ω) or 1 × 160 W BTL (8 Ω) class-D amplifier
[1] Pin BOOT should not be loaded by any other means than the boot capacitor. Shorting pin BOOT to V
SS
will damage the device.
[2] Pin STABI should not be loaded by an external circuit. Shorting pin STABI to a voltage source or V
SS
will damage the device.
[3] Pin DIAG should not be connected to a voltage source or to a pull-up resistor. An example of a circuit that can be used to read out
diagnostic data is given in Figure 7.
8. Thermal characteristics
9. Static characteristics
V
MODE
voltage on pin MODE referred to SGND2 0 8 V
V
OSC
voltage on pin OSC referred to V
SSD
040V
V
IN1M
voltage on pin IN1M referred to SGND1 −5+5V
V
IN1P
voltage on pin IN1P referred to SGND1 −5+5V
V
IN2M
voltage on pin IN2M referred to SGND2 −5+5V
V
IN2P
voltage on pin IN2P referred to SGND2 −5+5V
V
DIAG
voltage on pin DIAG referred to V
SSD
[3]
09V
V
O
output voltage V
SSP
− 0.3 V
DDP
+ 0.3 V
Table 5. Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Table 6. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-c)
thermal resistance from junction to case 1.1 K/W
R
th(j-a)
thermal resistance from junction to ambient in free air 35 K/W
Table 7. Static characteristics
V
P
=
±
27 V; f
osc
= 310 kHz; T
amb
=
−
40
°
C to +85
°
C; T
j
=
−
40
°
C to +150
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply
V
P
supply voltage
[1]
±14 ±27 ±29 V
I
q(tot)
total quiescent current no load, no filter, no snubber
network connected
- 5065mA
I
stb
standby current T
j
= −40 °C to +85 °C - 150 500 µA
Mode select input; pin MODE (reference to SGND2)
I
MODE
current on pin MODE V
MODE
= 5.5 V - 100 300 µA
V
MODE
voltage on pin mode Standby mode
[2][3]
0 - 0.8 V
Mute mode
[2][3]
2.2 - 2.8 V
Operating mode
[2][3]
4.2 - 6 V
Diagnostic output; pin DIAG (reference to V
SSD
)
V
OL
LOW-level output voltage activated OCP or WP
[4]
- - 0.8 V
V
OH
HIGH-level output voltage no activated OCP or WP
[4]
- 8.4 9 V
Audio inputs; pins IN1M, IN1P (reference to SGND1), IN2P and IN2M (reference to SGND2)
V
I
input voltage
[2]
-0 - V
TDF8590TH_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 23 April 2007 12 of 30
NXP Semiconductors
TDF8590TH
2 × 80 W SE (4 Ω) or 1 × 160 W BTL (8 Ω) class-D amplifier
[1] The circuit is DC adjusted at V
P
= ±12.5 V to ±30 V.
[2] Refers to usage in a symmetrical supply application (see Section 12.7). In an asymmetrical supply application the SGND voltage should
be defined by an external circuit.
[3] The transition between Standby and Mute mode contains hysteresis, while the slope of the transition between Mute and Operating
mode is determined by the time constant on pin MODE (see Figure 9).
[4] Pin DIAG should not be connected to an external pull-up.
[5] DC output offset voltage is applied to the output during the transition between Mute and Operating mode in a gradual way. The
dV
O(offset)
/dt caused by any DC output offset is determined by the time constant on pin MODE.
[6] At a junction temperature of approximately T
act(th_fold)
− 5 °C the gain reduction will commence and at a junction temperature of
approximately T
act(th_fold)
+ 5 °C the amplifier mutes.
Amplifier outputs; pins OUT1 and OUT2
V
O(offset)
output offset voltage SE; mute - - 20 mV
SE; operating
[5]
- - 170 mV
BTL; mute - - 30 mV
BTL; operating
[5]
- - 240 mV
Stabilizer output; pin STABI (reference to V
SSP1
)
V
O
output voltage mute and operating; with respect
to V
SSD
11 12.5 14 V
Temperature protection
T
prot
protection temperature - 160 180 °C
T
act(th_fold)
thermal foldback activation
temperature
closed loop SE voltage gain
reduced with 6 dB
[6]
145 150 - °C
Table 7. Static characteristics
…continued
V
P
=
±
27 V; f
osc
= 310 kHz; T
amb
=
−
40
°
C to +85
°
C; T
j
=
−
40
°
C to +150
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Fig 9. Behavior of pin MODE
STBY MUTE ON
5.5
001aad842
V
MODE
(V)
4.22.82.20.80
V
O(offset)
mute
operating
slope is directly related to the
time constant on pin MODE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

TDF8590TH/N1TJ

Mfr. #:
Buy TDF8590TH/N1TJ
Manufacturer:
NXP Semiconductors
Description:
Audio Amplifiers 2 X 80 W SE (4 ) or 1 X 160 W BTL (8 ) class-D amplifier
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet