ISL6504ACR-T Datasheet ISL6504CBZ, ISL6504CBZ-T, ISL6504ACRZ | P10-P12

FN9062.2

April 13, 2004

During sleep-to-active state transitions from conditions

where the 5V

DUAL

output is initially 0V (such as S5 to S0

transition, or simple power-up sequence directly into active

state), the circuit goes through a quasi soft-start, the 5V

DUAL

output

being pulled high through the body diode of the N-

Channel MOSFET connected between it and the 5V ATX.

Figure 9 exemplifies this start-up case. 5V

is already

present when the main ATX outputs are turned on, at time

T0. As a result of +5V

ramping up, the 5V

DUAL

output

capacitors charge up through the body diode of Q4 (see

Typical Application). At time T1, all main ATX outputs exceed

the ISL6504/A’s undervoltage thresholds, and the internal

25ms (typical) timer is initiated. At T2, the time-out initiates a

soft-start, and the 1.2V voltage ID output is ramped-up,

reaching regulation limits at time T3. Simultaneous with the

beginning of this ramp-up, at time T2, the DLA pin is

released, allowing the pull-up resistor to turn on Q2 and Q4,

and bring the 5V

DUAL

output in regulation. Shortly after time

T3, as the SS voltage reaches 2.75V, the soft-start capacitor

is quickly discharged down to approximately 2.45V, where it

remains until a valid sleep state request is received from the

system.

Fault Protection

All the outputs are monitored against undervoltage events. A

severe overcurrent caused by a failed load on any of the

outputs, would, in turn, cause that specific output to

suddenly drop. If any of the output voltages drops below

80% (typical) of their set value, such event is reported by

having the FAULT pin pulled to 5V. Additionally, exceeding

the maximum current rating of an integrated regulator

(output with pass regulator on chip) can lead to output

voltage drooping; if excessive, this droop can ultimately trip

the undervoltage detector and send a FAULT signal to the

computer system.

A FAULT condition occurring on an output when controlled

through an external pass transistor will only set off the

FAULT flag, and it will not shut off or latch off any part of the

circuit. A FAULT condition occurring on an output controlled

through an internal pass transistor, will set off the FAULT

flag, and it will shut off the respective faulting regulator only.

If shutdown or latch off of the entire circuit is desired in case

of a fault, regardless of the cause, this can be achieved by

externally pulling or latching the SS pin low. Pulling the SS

pin low will also force the FAULT pin to go low and reset any

internally latched-off output.

Special consideration is given to the initial start-up

sequence. If, following a 5V

POR event, any of the

1.5V

or 3.3V

DUAL

/3.3V

outputs is ramped up and is

subject to an undervoltage event before the end of the

second soft-start ramp, then the FAULT output goes high

and the entire IC latches off. Latch-off condition can be reset

by cycling the bias power (5V

). Undervoltage events on

the 1.5V

and the 3.3V

DUAL

/3.3V

outputs at any other

times are handled according to the description found in the

second paragraph under the current heading.

Another condition that could set off the FAULT flag is chip

overtemperature. If the ISL6504/A reaches an internal

temperature of 140

C (typical), the FAULT flag is set, but the

chip continues to operate until the temperature reaches

155

C (typical), when unconditional shutdown of all outputs

takes place. Operation resumes only after powering down

the IC (to create a 5V

POR event) and a start-up

(assuming the cause of the fault has been removed; if not,

as it heats up again, it will repeat the FAULT cycle).

In ISL6504/A applications, loss of the active ATX output

(3.3V

; as detected by the on-board voltage monitor) during

active state operation causes the chip to switch to S5 sleep

state, in addition to reporting the input UV condition on the

FAULT pin. Exiting from this forced S5 state can only be

achieved by returning the faulting input voltage above its UV

threshold, by resetting the chip through removal of 5V

bias voltage, or by bringing the SS pin at a potential lower

than 0.8V.

Application Guidelines

Soft-Start Interval

The 5V

output of a typical ATX supply is capable of

725mA, with newer models rated for 1.0A, and even 2.0A.

During power-up in a sleep state, the 5V

ATX output

needs to provide sufficient current to charge up all the

applicable output capacitors and, simultaneously, provide

some amount of current to the output loads. Drawing

FIGURE 9. SOFT-START INTERVAL IN ACTIVE STATE

TIME

OUTPUT

(1V/DIV)

VOLTAGES

T1 T2

INPUT VOLTAGES

(2V/DIV)

+5VIN

+12VIN

+5VSB

VOUT1 (1.5VSB)

VOUT3 (3.3VDUAL/3.3VSB)

VOUT4 (5VDUAL)

DLA PIN

(2V/DIV)

+3.3VIN

VOUT2 (1.2VVID)

SOFT-START

(1V/DIV)

ISL6504, ISL6504A

FN9062.2

April 13, 2004

excessive amounts of current from the 5V

output of the

ATX can lead to voltage collapse and induce a pattern of

consecutive restarts with unknown effects on the system’s

behavior or health.

The built-in soft-start circuitry allows tight control of the slew-

up speed of the output voltages controlled by the ISL6504,

thus enabling power-ups free of supply drop-off events.

Since the outputs are ramped up in a linear fashion, the

current dedicated to charging the output capacitors can be

calculated with the following formula:

, where

- soft-start current (typically 10A)

- soft-start capacitor

- bandgap voltage (typically 1.26V)

C

OUT

x V

OUT

) - sum of the products between the

capacitance and the voltage of an output (total charge

delivered to all outputs)

Due to the various system timing events and their

interaction, it is recommended that the soft-start interval not

be set to exceed 30ms. For most applications, a 0.1F

capacitor is recommended.

Shutdown

In case of a FAULT condition that might endanger the

computer system, or at any other time, all the ISL6504/A

outputs can be shut down by pulling the SS pin below the

specified shutdown level (typically 0.8V) with an open drain

or open collector device capable of sinking a minimum of

2mA. Pulling the SS pin low effectively shuts down all the

pass elements. Upon release of the SS pin, the ISL6504

undergoes a new soft-start cycle and resumes normal

operation in accordance to the ATX supply and control pins

status.

VID_PG Delay

During power-up and initial soft-start, the VID_PG and

VID_CT pins are held low. As the 1V2VID output exceeds its

rising power-good threshold, the capacitor connected at the

VID_CT pin starts to charge up through the internal 10A

current source. As the voltage on this capacitor exceeds

1.25V, the open-collector VID_PG pin is released and VID

POWER GOOD status is thus reported.

The value of the VID_CT capacitor to be used to obtain a

given VID_PG delay can be determined from the graph in

Figure 10. For extended delays exceeding the range of the

graph, use the following formula:

, where

DELAY

- desired delay time (s)

C - VID_CT capacitor to obtain desired delay time (F)

Layout Considerations

The typical application employing an ISL6504/A is a fairly

straight forward implementation. Like with any other linear

regulator, attention has to be paid to the few potentially

sensitive small signal components, such as those connected

to sensitive nodes or those supplying critical bypass current.

The power components (pass transistors) and the controller

IC should be placed first. The controller should be placed in

a central position on the motherboard, closer to the memory

controller chip and processor, but not excessively far from

the 3.3V

DUAL

island or the I/O circuitry. Ensure the 1V5SB,

1V2VID, 3V3, and 3V3DL connections are properly sized to

carry 100mA without exhibiting significant resistive losses at

the load end. Similarly, the input bias supply (5V

) can

carry a significant level of current - for best results, ensure it

is connected to its respective source through an adequately

sized trace. The pass transistors should be placed on pads

capable of heatsinking matching the device’s power

dissipation. Where applicable, multiple via connections to a

large internal plane can significantly lower localized device

temperature rise.

Placement of the decoupling and bulk capacitors should

follow a placement reflecting their purpose. As such, the

high-frequency decoupling capacitors should be placed as

close as possible to the load they are decoupling; the ones

decoupling the controller close to the controller pins, the

ones decoupling the load close to the load connector or the

load itself (if embedded). Even though bulk capacitance

(aluminum electrolytics or tantalum capacitors) placement is

not as critical as the high-frequency capacitor placement,

having these capacitors close to the load they serve is

preferable.

The critical small signal components include the soft-start

capacitor, C

, as well as all the high-frequency decoupling

capacitors. Locate these components close to the respective

COUT



------------------------------

 C

OUT

=

DELAY

125000

--------------------

C (nF)

FIGURE 10. VID_PG DELAY DEPENDENCE ON VID_CT

CAPACITOR

VID_PG Delay (ms)

123

78910

ISL6504, ISL6504A

FN9062.2

April 13, 2004

pins of the control IC, and connect them to ground through a

via placed close to the ground pad. Minimize any leakage

current paths from the SS node, as the internal current

source is only 10A (typical).

A multi-layer printed circuit board is recommended.

Figure 11 shows the connections to most of the components

in the circuit. Note that the individual capacitors shown each

could represent numerous physical capacitors. Dedicate one

solid layer for a ground plane and make all critical

component ground connections through vias placed as close

to the component terminal as possible. Dedicate another

solid layer as a power plane and break this plane into

smaller islands of common voltage levels. Ideally, the power

plane should support both the input power and output power

nodes. Use copper filled polygons on the top and bottom

circuit layers to create power islands connecting the filtering

components (output capacitors) and the loads. Use the

remaining printed circuit layers for small signal wiring.

Component Selection Guidelines

Output Capacitors Selection

The output capacitors should be selected to allow the output

voltage to meet the dynamic regulation requirements of

active state operation (S0, S1). The load transient for the

various microprocessor system’s components may require

high quality capacitors to supply the high slew rate (di/dt)

current demands. Thus, it is recommended that the output

capacitors be selected for transient load regulation, paying

attention to their parasitic components (ESR, ESL).

Also, during the transition between active and sleep states

on the 3.3V

DUAL

/3.3V

and 5V

DUAL

outputs, there is a

short interval of time during which none of the power pass

elements are conducting - during this time the output

capacitors have to supply all the output current. The output

voltage drop during this brief period of time can be easily

approximated with the following formula:

, where

V

OUT

- output voltage drop

ESR

OUT

- output capacitor bank ESR

OUT

- output current during transition

OUT

- output capacitor bank capacitance

- active-to-sleep or sleep-to-active transition time (10s typ.)

The output voltage drop is heavily dependent on the ESR

(equivalent series resistance) of the output capacitor bank,

the choice of capacitors should be such as to maintain the

output voltage above the lowest allowable regulation level.

Input Capacitors Selection

The input capacitors for an ISL6504/A application must have

a sufficiently low ESR so as not to allow the input voltage to

dip excessively when energy is transferred to the output

capacitors. If the ATX supply does not meet the

specifications, certain imbalances between the ATX’s

outputs and the ISL6504/A’s regulation levels could have as

a result a brisk transfer of energy from the input capacitors to

the supplied outputs. At the transition between active and

sleep states, such phenomena could be responsible for the

voltage drooping excessively and affecting the output

regulation. The solution to such a potential problem is using

larger input capacitors with a lower total combined ESR.

Transistor Selection/Considerations

The ISL6504/A usually requires one P-Channel (or bipolar

PNP), two N-Channel MOSFETs, and one bipolar NPN

transistors.

One important criteria for selection of transistors for all the

linear regulators/switching elements is package selection for

efficient removal of heat. The power dissipated in a linear

regulator or an ON/OFF switching element is

Select a package and heatsink that maintains the junction

temperature below the rating with the maximum expected

ambient temperature.

LOAD

VOUT1

CHF1

LOAD

FIGURE 11. PRINTED CIRCUIT BOARD ISLANDS

VOUT3

CSS

+12VIN

CIN

VIA CONNECTION TO GROUND PLANE

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT/POWER PLANE LAYER

ISL6504/A

VOUT4

GND

5VDLSB

3V3DLSB

KEY

5VSB

+5VSB

DLA

CBULK4

LOAD

C5VSB

LOAD

CHF3

CHF4

5VDL

+5VIN

+3.3VIN

3V3DL

3V3

1V5SB

CBULK2

CHF2

CBULK1

1V2VID

CBULK3

VOUT2

OUT

 I

OUT

ESR

OUT

----------------







=

LINEAR

OUT

–=

ISL6504, ISL6504A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

ISL6504ACR-T

Mfr. #:

Buy ISL6504ACR-T

Manufacturer:

Renesas / Intersil

Description:

IC MULTIPLE POWER CTRLR 20-QFN

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ISL6504ACR-T

ISL6504ACR-T

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