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ISL6504ACR-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
13
FN9062.2
April 13, 2004
Q1
The NPN transistor used as sleep state pass element on the
3.3V
DUAL
output has to have a minimum current gain of 100
at 1.5V V
CE
and 650mA I
CE
throughout the in-circuit
operating temperature range. For larger current ratings on
the 3.3V
DUAL
output (providing the ATX 5V
SB
output rating
is equally extended), selection criteria for Q1 include an
appropriate current gain (h
fe
) and saturation characteristics.
Q2, Q4
These N-Channel MOSFETs are used to switch the 3.3V
and 5V inputs provided by the ATX supply into the
3.3V
DUAL
/3.3V
SB
and 5V
DUAL
outputs while in active (S0,
S1) state. The main criteria for the selection of these
transistors is output voltage budgeting. The maximum
r
DS(ON)
allowed at highest junction temperature can be
expressed with the following equation:
, where
V
INmin
- minimum input voltage
V
OUTmin
- minimum output voltage allowed
I
OUTmax
- maximum output current
Q3
If a P-Channel MOSFET is used to switch the 5V
SB
output of
the ATX supply into the 5V
DUAL
output during sleep states,
then the selection criteria of this device is proper voltage
budgeting. The maximum r
DS(ON)
, however, has to be
achieved with only 4.5V of gate-to-source voltage, so a logic
level MOSFET needs to be selected. If a PNP device is
chosen to perform this function, it has to have a low-
saturation voltage while providing the maximum sleep
current and have a current gain sufficiently high to be
saturated using the minimum drive current (typically 20mA).
ISL6504 Application Circuit
Figure 12 shows a typical application circuit for the
ISL6504/A. The circuit provides the 3.3V
DUAL
/3.3V
SB
voltage, the ICH4 resume well 1.5V
SB
voltage, the 1.2V
VID
voltage identification output, and the 5V
DUAL
keyboard/mouse voltage from +3.3V, +5V
SB
, +5V, and
+12VDC ATX supply outputs. Q3 can also be a PNP
transistor, such as an MMBT2907AL. For additional, more
detailed information on the circuit, including a Bill-of-
Materials and circuit board description, see Application Note
AN1001. Also see Intersil Corporation’s web page
(www.intersil.com).
r
DS ONmax
V
INmin
V
OUTmin
–
I
OUTmax
---------------------------------------------------
=
FIGURE 12. TYPICAL ISL6504/A APPLICATION DIAGRAM
C1
1mF
220mF
330mF
GND
5VSB
S3
ISL6504/A
S5
+3.3VDUAL/3.3VSB
C6
+5VDUAL
3V3DL
3V3DLSB
Q1
Q3
Q4
DLA
5VDLSB
FAULT
5VDL
SS
+
+
2SD1802
FDV304P
HUF76113T3S
C4
U1
+5VSB
+5VIN
+12VIN
+3.3VIN
‘FAULT’
3V3
16
1
2
3
4
5
6
7
8
9
10
11
12
13
+1.5VSB
Q2
HUF76113T3S
1V5SB
10mF
1V2VID
C3
+
+1.2VVID
10mF
C5
+
R1
1k
14
VID_PG
‘VID PGOOD’
R2
10k
15
VID_CT
C2
0.1mF
C7
0.1mF
S3
S5
R3
1k
ISL6504, ISL6504A
14
FN9062.2
April 13, 2004
ISL6504, ISL6504A
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
µ
0.25(0.010) BM M
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
15
FN9062.2
April 13, 2004
ISL6504, ISL6504A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L20.6x6
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VJJB ISSUE C)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.28 0.33 0.40 5, 8
D 6.00 BSC -
D1 5.75 BSC 9
D2 3.55 3.70 3.85 7, 8
E 6.00 BSC -
E1 5.75 BSC 9
E2 3.55 3.70 3.85 7, 8
e 0.80 BSC -
k0.25 - - -
L 0.35 0.60 0.75 8
L1 - - 0.15 10
N202
Nd 5 3
Ne 5 3
P- -0.609
--129
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ISL6504ACR-T

Mfr. #:
Buy ISL6504ACR-T
Manufacturer:
Renesas / Intersil
Description:
IC MULTIPLE POWER CTRLR 20-QFN
Lifecycle:
New from this manufacturer.
Delivery:
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