13
FN6538.2
December 2, 2008
.
Figure 11 shows the critical power components of the
converter. To minimize the voltage overshoot, the
interconnecting wires indicated by heavy lines should be part of
a ground or power plane in a printed circuit board. The
components shown should be located as close together as
possible. Please note that the capacitors C
IN
and C
O
may each
represent numerous physical capacitors. For best results,
locate the ISL6341x within 1 inch of the MOSFETs, Q
1
and Q
2
.
The circuit traces for the MOSFET gate and source
connections from the ISL6341x must be sized to handle up to
2A peak current.
Figure 12 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Provide local V
CC
decoupling between VCC and GND pins. Locate the
capacitor, C
BOOT
as close as practical to the BOOT and
PHASE pins. Locate the resistor, R
OSCET
close to the
LGATE/OCSET pin because the internal current source is
only 10µA. Minimize any leakage current paths on the
COMP/EN pin. All components used for feedback
compensation and VOS resistor divider (inside the dotted
box) should be located as close to the IC as practical. Near
the load, pick a point V
OUT
that will be the regulation center;
run a single unloaded narrow trace from there to the
compensation components. The same trace can also be
used for VOS divider.
Feedback Compensation
This section highlights the design consideration for a
voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended, as shown in the top part of
Figure 13.
Figure 13 also highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable to the
ISL6341x circuit. The output voltage (V
OUT
) is regulated to
the reference voltage, V
REF
. The error amplifier output
(COMP pin voltage) is compared with the oscillator (OSC)
modified sawtooth wave to provide a pulse-width modulated
wave with an amplitude of V
IN
at the PHASE node. The
PWM wave is smoothed by the output filter (L and C). The
output filter capacitor bank’s equivalent series resistance is
represented by the series resistor E.
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
COMP
. This function is dominated by a DC
gain, given by d
MAX
V
IN
/V
OSC
, and shaped by the output
filter, with a double pole break frequency at F
LC
and a zero at
F
CE
. For the purpose of this analysis, L and D represent the
channel inductance and its DCR, while C and E represent the
total output capacitance and its equivalent series resistance.
L
O
C
O
LGATE/OCSET
UGATE
PHASE
Q
1
Q
2
V
IN
V
OUT
RETURN
ISL6341x
C
IN
LOAD
FIGURE 11. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
FIGURE 12. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
+V
CC
ISL6341x
LGATE/OCSET
GND
VCC
BOOT
L
O
C
O
V
OUT
LOAD
Q
1
Q
2
PHASE
+V
IN
C
BOOT
R
OCSET
+V
GD
C
VCC
FB
COMP/EN
VOS
V
OUT
F
LC
1
2π LC
---------------------------
=
F
CE
1
2π CE⋅⋅
------------------------
=
(EQ. 3)
FIGURE 13. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
-
+
E/A
VREF
COMP
C1
R2
R1
FB
C2
R3
C3
L
C
V
IN
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
OSCILLATOR
E
EXTERNAL CIRCUIT
ISL6341x
V
OUT
V
OSC
D
UGATE
LGATE
Ro
PHASE
ISL6341, ISL6341A, ISL6341B, ISL6341C
14
FN6538.2
December 2, 2008
The compensation network consists of the error amplifier
(internal to the ISL6341x) and the external R
1
to R
3
, C
1
to C
3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
0
; typically 0.1 to 0.3 of f
SW
) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F
0dB
and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R
1
, R
2
, R
3
, C
1
, C
2
, and
C
3
) in Figure 13. Use the following guidelines for locating the
poles and zeros of the compensation network:
4. Select a value for R
1
(1kΩ to 5kΩ, typically). Calculate the
value for R
2
for desired converter bandwidth (F
0
). If
setting the output voltage via an offset resistor connected
to the FB pin (R
o
in Figure 13), the design procedure can
be followed as presented in Equation 4.
5. Calculate C
1
such that F
Z1
is placed at a fraction of the F
LC
,
at 0.1 to 0.75 of F
LC
(to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
CE
/F
LC
, the lower the F
Z1
frequency (to maximize phase boost at F
LC
).
6. Calculate C
2
such that F
P1
is placed at F
CE
.
7. Calculate R
3
such that F
Z2
is placed at F
LC
. Calculate C
3
such that F
P2
is placed below f
SW
(typically, 0.5 to 1.0
times f
SW
). f
SW
represents the switching frequency.
Change the numerical factor to reflect desired placement
of this pole. Placement of F
P2
lower in frequency helps
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. Equations 8 and 9 describe the
frequency response of the modulator (G
MOD
), feedback
compensation (G
FB
) and closed-loop response (G
CL
):
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 14 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previous guidelines should yield
a compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
P2
against the capabilities of the error
amplifier. The closed loop gain, G
CL
, is constructed on the log-
log graph of Figure 14 by adding the modulator gain, G
MOD
(in
dB), to the feedback compensation gain, G
FB
(in dB). This is
equivalent to multiplying the modulator transfer function and the
compensation transfer function and then plotting the resulting
gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
R
2
V
OSC
R
1
F
0
⋅⋅
d
MAX
V
IN
F
LC
⋅⋅
---------------------------------------------
=
(EQ. 4)
C
1
1
2π R
2
0.5 F
LC
⋅⋅
-----------------------------------------------
=
(EQ. 5)
C
2
C
1
2π R
2
C
1
F
CE
1⋅⋅⋅
--------------------------------------------------------
=
(EQ. 6)
R
3
R
1
f
SW
F
LC
-----------
1
--------------------
=
C
3
1
2π R
3
0.7 f
SW
⋅⋅
-----------------------------------------------
=
(EQ. 7)
G
MOD
f()
d
MAX
V
IN
V
OSC
------------------------------
1sf() EC⋅⋅+
1sf() ED+()C⋅⋅s
2
f() LC⋅⋅++
----------------------------------------------------------------------------------------
=
G
FB
f()
1sf() 2
R
1
C
⋅⋅+
sf() 1
R
1
C
2
C
+()⋅⋅
---------------------------------------------------
=
1sf() 1
R
3
R
+()3
C
⋅⋅+
1sf() 3
R
3
C
⋅⋅+()1sf() 2
R
1
C
2
C
1
C
2
C
+
--------------------
⎝⎠
⎜⎟
⎛⎞
⋅⋅+
⎝⎠
⎜⎟
⎛⎞
------------------------------------------------------------------------------------------------------------------------
G
CL
f() G
MOD
f() G
FB
f()=
where s f(), 2π fj⋅⋅=
(EQ. 8)
F
Z1
1
2π 2
R
1
C
⋅⋅
------------------------------
=
F
Z2
1
2π 1
R
3
R
+()3
C
⋅⋅
------------------------------------------------
=
F
P1
1
2π 2
R
1
C
2
C
1
C
2
C
+
--------------------
⋅⋅
--------------------------------------------
=
F
P2
1
2π 3
R
3
C
⋅⋅
------------------------------
=
(EQ. 9)
0
F
P1
F
Z2
OPEN LOOP E/A GAIN
F
Z1
F
P2
F
LC
F
CE
COMPENSATION GAIN
GAIN
FREQUENCY
MODULATOR GAIN
FIGURE 14. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
CLOSED LOOP GAIN
20
2
R
1
R
--------
⎝⎠
⎜⎟
⎜⎟
⎛⎞
log
LOG
LOG
F
0
G
MOD
G
FB
G
CL
20
d
MAX
V
IN
V
OSC
---------------------------------log
ISL6341, ISL6341A, ISL6341B, ISL6341C
15
FN6538.2
December 2, 2008
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, f
SW
.
This is just one method to calculate compensation components;
there are variations of the compensation break frequency
equations. The error amp is similar to that on other Intersil
regulators, so existing tools can be used here as well. Special
consideration is needed if the size of a ceramic output
capacitance in parallel with bulk capacitors gets too large; the
calculation needs to model them both separately (attempting to
combine two different capacitors types into one composite
component model may not work properly; a special tool may be
needed; contact your local Intersil person for assistance).
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern components and loads are capable of producing
transient load rates above 1A/ns. High frequency capacitors
initially supply the transient and slow the current load rate
seen by the bulk capacitors. The bulk filter capacitor values
are generally determined by the ESR (Effective Series
Resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by Equation 10:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6341x will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval, the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. Equation 11
gives the approximate response time interval for application
and removal of a transient load:
where: I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check Equation 11 at the minimum and
maximum output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q
1
turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q
1
and the source of Q
2
.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25x greater than the maximum input
voltage and a voltage rating of 1.5x is a conservative
guideline. The RMS current rating requirement for the input
capacitor of a buck regulator is approximately 1/2 the DC
load current.
ΔI =
V
IN
- V
OUT
Fsw x L
V
OUT
V
IN
ΔV
OUT
= ΔI x ESR
x
(EQ. 10)
t
RISE
=
L x I
TRAN
V
IN
- V
OUT
t
FALL
=
L x I
TRAN
V
OUT
(EQ. 11)
ISL6341, ISL6341A, ISL6341B, ISL6341C

ISL6341CCRZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 10LD 3X3 SYNCH PWM BUCK CONT 5V OR 12V
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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