16
FN6538.2
December 2, 2008
For a through-hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can also be used, but caution must be exercised
with regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
MOSFET Selection/Considerations
The ISL6341x requires 2 N-Channel power MOSFETs. These
should be selected based upon r
DS(ON)
, gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor. The switching
losses seen when sourcing current will be different from the
switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching
losses. The lower switch realizes most of the switching losses
when the converter is sinking current (see Equation 12).
Equation 12 assumes linear voltage-current transitions and
does not adequately model power loss due to the reverse-
recovery of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated by the ISL6341x and don't
heat the MOSFETs. However, large gate-charge increases the
switching interval, t
SW
which increases the MOSFET switching
losses. Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may be
necessary depending upon MOSFET power, package type,
ambient temperature and air flow.
When operating with a 12V power supply for V
CC
(or down
to a minimum supply voltage of 4.5V), a wide variety of
N-MOSFETs can be used. Check the absolute maximum
V
GS
rating for both MOSFETs; it needs to be above the
highest V
CC
voltage allowed in the system; that usually
means a 20V V
GS
rating (which typically correlates with a
30V V
DS
maximum rating). Low threshold transistors
(around 1V or below) are not recommended, as explained in
the following.
For 5V only operation, given the reduced available gate bias
voltage (5V), logic-level transistors should be used for both
N-MOSFETs. Look for r
DS(ON)
ratings at 4.5V. Caution
should be exercised with devices exhibiting very low
V
GS(ON)
characteristics. The shoot-through protection
present aboard the ISL6341x may be circumvented by these
MOSFETs if they have large parasitic impedences and/or
capacitances that would inhibit the gate of the MOSFET from
being discharged below its threshold level before the
complementary MOSFET is turned on. Also avoid MOSFETs
with excessive switching times; the circuitry is expecting
transitions to occur in under 50ns or so.
BOOTSTRAP Considerations
Figure 15 shows the upper gate drive (BOOT pin) supplied
by a bootstrap circuit from V
GD
. For convenience, V
GD
usually shares the V
IN
or V
CC
supply; it can be any voltage
in the 5V to 12V range. The boot capacitor, C
BOOT
,
develops a floating supply voltage referenced to the PHASE
pin. The supply is refreshed to a voltage of V
GD
less the
boot diode drop (V
D
) each time the lower MOSFET, Q
2
,
turns on. Check that the voltage rating of the capacitor is
above the maximum V
CC
voltage in the system; a 16V rating
should be sufficient for a 12V system. A value of 0.1µF is
typical for many systems driving single MOSFETs.
If V
CC
is 12V, but V
IN
is lower (such as 5V), then another
option is to connect the BOOT pin to 12V, and remove the
BOOT cap (although, you may want to add a local capacitor
from BOOT to GND). This will make the UGATE V
GS
voltage
equal to (12V - 5V = 7V). That should be high enough to
drive most MOSFETs, and low enough to improve the
efficiency slightly. This also saves a boot diode and
capacitor.
P
LOWER
= Io
2
x r
DS(ON)
x (1 - D)
Where: D is the duty cycle = V
OUT
/ V
IN
,
t
SW
is the combined switch ON and OFF time, and
f
SW
is the switching frequency.
Losses while Sourcing Current
Losses while Sinking Current
P
LOWER
Io
2
r
DS ON()
× 1D–()×
1
2
---
Io⋅ V
IN
× t
SW
F
S
××+=
P
UPPER
Io
2
r
DS ON()
× D×
1
2
---
Io⋅ V
IN
× t
SW
F
S
××+=
P
UPPER
= Io
2
x r
DS(ON)
x D
(EQ. 12)
+V
CC
ISL6341x
GND
LGATE/OCSET
UGATE
PHASE
BOOT
VCC
+V
IN
V
G-S
≈ V
GD
- V
D
V
G-S
≈ V
CC
C
BOOT
Q1
Q2
+
-
FIGURE 15. UPPER GATE DRIVE BOOTSTRAP
VCC
+V
GD
- V
D
+
ISL6341, ISL6341A, ISL6341B, ISL6341C
