ISL6341CCRZ-T Datasheet ISL6341CRZ, ISL6341ACRZ, ISL6341IRZ | P7-P9

FN6538.2

December 2, 2008

From t1, there is a nominal 4ms delay, which allows the VCC

pin to rise. At the same time, the LGATE/OCSET pin is

initialized by disabling the LGATE driver and drawing I

OCSET

(nominal 10µA) through R

OCSET

. This sets up a voltage that

will represent the OCSET trip point for the OCP sample and

hold operation. The sample and hold uses a digital counter and

DAC (to save the voltage so the stored value does not degrade)

for as long as the V

is above V

POR

. See “Overcurrent

Protection (OCP)” on page 8 for more details on the equations

and variables. Upon the completion of sample and hold at t2,

the soft-start operation is initiated (around 0.8ms delay to t3),

and then around 4ms for the output voltage to ramp up (0% to

100%) between t3 and t4. The PGOOD output is allowed to go

high at t4 if VOS (and thus V

OUT

) is within the PGOOD

window.

Soft-Start and Pre-Biased Outputs

Functionally, the soft-start internally ramps the reference on the

non-inverting terminal of the error amp from zero to 0.8V in a

nominal 4ms. The output voltage will thus follow the ramp, from

zero to final value, in the same 4ms. The ramp is created

digitally, so there will be small discrete steps. There is no simple

way to change this ramp rate externally, as it is fixed by the

300kHz (or 600kHz) switching frequency (and the ramp and

delay time is the same for both frequencies).

After an initialization period (t2 to t3), the error amplifier

(COMP/EN pin) is enabled, and begins to regulate the

converter’s output voltage during soft-start. The oscillator’s

triangular waveform is compared to the ramping error amplifier

voltage. This generates PHASE pulses of increasing width that

charge the output capacitors. When the internally generated

soft-start voltage exceeds the reference voltage (0.8V), the

soft-start is complete, and the output should be in regulation at

the expected voltage. This method provides a rapid and

controlled output voltage rise; there is no large in-rush current

charging the output capacitors. The entire start-up sequence

from POR typically takes 9ms; 5ms for the delay and OCP

sample, and 4ms for the soft-start ramp.

Figure 3 shows the normal V

OUT

curve in blue; initialization

begins at t0, and the output ramps between t1 and t2. If the

output is pre-biased to a voltage less than the expected

value (as shown by the magenta curve), the ISL6341x will

detect that condition. Neither MOSFET will turn-on until the

soft-start ramp voltage exceeds the output; V

OUT

starts

seamlessly ramping from there.

There is a restriction for the pre-bias case; if the pre-biased

OUT

is greater than V

, then the boot cap may get

discharged, and will not be able to restart. For example, if

= 12V, V

OUT

= 8V and prebiased to 6V, and V

is only

5V, then the voltage left on the boot cap (to UGATE) will not

be able to turn on the upper FET. The simple solution here is

to use the 12V for V

. The guideline is to make V

diode - Vth upper FET > V

OUT

to prevent this condition.

If the output is pre-biased to a voltage above the expected

value (as in the red curve), neither MOSFET will turn-on until

the end of the soft-start, at which time it will pull the output

voltage quickly down to the final value. Any resistive load

connected to the output will help pull-down the voltage (at

the RC rate of the R of the load and the C of the output

capacitance).

One exception to the overcharged case is if the pre-bias is

high enough to trip OV protection (>1V on VOS); then

LGATE will pulse to try to pull V

OUT

lower. The IC will remain

latched in this mode until V

power is toggled.

If the V

to the upper MOSFET drain (or the V

voltage to

the boot diode) is from a different supply that comes up after

, the soft-start would start its cycle, but with no output

voltage ramp. Once the undervoltage protection is enabled

(at the end of the soft-start ramp), the output will latch off.

Therefore, for normal operation, V

(and V

) must be high

enough before or with V

. If this is not possible, then the

alternative is add sequencing logic to the COMP/EN pin to

delay the soft-start until the V

(and V

) supply is ready

(see “Input Voltage Considerations” on page 12).

LGATE

STARTS

SWITCHING

4.0ms

OUT

(0.25V/DIV)

GND>

t0 t1 t2 t3 t4

0.8ms 4.0ms

COMP/EN (0.25V/DIV)

0.25V/DIV

LGATE/OCSET

0.7V

PGOOD (2V/DIV)

FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION

FIGURE 3. SOFT-START WITH PRE-BIAS

GND>

OUT

NORMAL

GND>GND>

OUT

PRE-BIASED

OUT

OVERCHARGED

t0 t1 t2

ISL6341, ISL6341A, ISL6341B, ISL6341C

FN6538.2

December 2, 2008

If the IC is disabled after soft-start (by pulling COMP/EN pin

low), and then enabled (by releasing the COMP/EN pin),

then the full initialization (including a new OCP sample) will

take place.

If the output is shorted to GND during soft-start, the OCP will

handle it, as described in the next section.

Overcurrent Protection (OCP)

The overcurrent function protects the converter from a shorted

output by using the lower MOSFET’s ON-resistance, r

DS(ON)

to monitor the current. A resistor (R

OCSET

) programs the

overcurrent trip level (see “Typical Application” on page 3).

This method enhances the converter’s efficiency and reduces

cost by eliminating a current sensing resistor.

Following POR and release of COMP/EN, the ISL6341x

initiates the Overcurrent Protection sample and hold

operation. The LGATE driver is disabled to allow an internal

10µA current source to develop a voltage across R

OCSET

The ISL6341x samples this voltage (which is referenced to

the GND pin) at the LGATE/OCSET pin, and holds it in a

counter and DAC combination. This sampled voltage is held

internally as the Overcurrent Set Point, for as long as power

is applied, or until a new sample is taken after coming out of

a COMP/EN shut-down.

The actual monitoring of the lower MOSFET’s ON-resistance

starts 200ns (nominal) after the edge of the internal PWM logic

signal (that creates the rising external LGATE signal). This is

done to allow the gate transition noise and ringing on the

PHASE pin to settle out before monitoring. The monitoring

ends when the internal PWM edge (and thus LGATE) goes low.

The OCP can be detected anywhere within the above window.

To allow sufficient time to detect OCP, the regulator will limit

the maximum UGATE duty cycle to ~85% at 300kHz (~75%

at 600kHz); there will always be an LGATE pulse of at least

300ns. This minimum width will also act as a boot-refresh

function. If the boot capacitor loses any charge while UGATE

is high, it will be refreshed each cycle while LGATE is high.

The ISL6341x share most of the detection circuitry; the main

difference among them is what happens after detection.

ISL6341, ISL6341B

When overcurrent is detected (while LGATE is high), the logic

will disable UGATE, and leave LGATE high until the current

drops to 1/2 of its programmed OCP value. This may take

several clock cycles, and it keeps the current from building up

too high. Once the current is low enough, UGATE will go high

on the next PWM cycle, and OCP will be monitored when

LGATE goes high. If OCP trips a 2nd time, it will again wait

until the current drops. If it trips for the 3rd time, it will latch off

the output (LGATE and UGATE low). If there is no OCP trip on

one of the retries, then the trip-counter resets to zero, and

three new consecutive cycles are required to latch off.

Figure 4 shows a typical waveform for the ISL6341,

ISL6341B, where the normal inductor current is around 10A,

and the OCP trip is 16A. This is just an illustration; the actual

shape of the waveforms depends on the component values,

as well as the characteristics of the load and the short. On the

third trip, the gate drivers stop switching, and the current goes

to zero. To recover from this latched off condition, the user

must toggle V

(power-down and power-up) for a new POR,

or toggle COMP/EN pin to restart (either includes initialization

and soft-start).

As the output inductor current rises and falls, the output

voltage is also affected. Note that in extreme cases during

the three consecutive trips, the UV may actually trip before

the OCP. The IC provides protection in either case, but

perhaps not quite at the programmed current. An OCP trip

can be reset by toggling either POR or COMP/EN, but a UV

trip is only reset by toggling POR. See Table 2 for the

protection summary.

Starting up into a shorted load will be handled the same way;

but the waveforms may look different, since the output is not

yet at its final value. OCP is always enabled during soft-start

(UV is not); it will need the three consecutive trips to latch off.

ISL6341A, ISL6341C

Figure 5 shows the same conditions for the ISL6341A,

ISL6341C. For this version, when overcurrent is first

detected (while LGATE is high), the logic will shut off the

output (LGATE and UGATE both go low), and the current

goes to zero.

It will then go into a “hiccup” mode of infinite retries. After two

dummy soft-start time-outs, a real soft-start will begin. If the

short is still there, it will trip during the soft-start ramp, and

will start another retry cycle. Once the short is removed, the

next real soft-start will be successful, and normal operation

can continue.

FIGURE 4. OCP TIMING (ISL6341, ISL6341B)

UGATE (24V/DIV)

0A>

GND>

INDUCTOR

(10A/DIV)

1/2 OC

GND>

LGATE (12V/DIV)

ISL6341, ISL6341A, ISL6341B, ISL6341C

FN6538.2

December 2, 2008

Figure 6 shows the ISL6341A, ISL6341C output response

during a retry of an output shorted to GND. At time t0, the

output has been turned off, due to sensing an overcurrent

condition. There are two internal soft-start delay cycles (t1

and t2) to allow the MOSFETs to cool down, to keep the

average power dissipation in retry at an acceptable level. At

time t2, the output starts a normal soft-start cycle, and the

output tries to ramp. If the short is still applied, and the

current reaches the OCSET trip point any time during

soft-start ramp period, the output will shut off and return to

time t0 for another delay cycle. The retry period is thus two

dummy soft-start cycles plus one variable one, which

depends on how long it takes to trip the sensor each time.

Figure 6 shows an example where the output gets about

half-way up before shutting down; therefore, the retry (or

hiccup) time will be around 12ms. The minimum should be

nominally 9.6ms and the maximum 14.4ms. If the short

condition is finally removed, the output should ramp up

normally on the next t2 cycle.

Starting up into a shorted load looks the same as a retry into

that same shorted load. In both cases, OCP is always

enabled during soft-start; once it trips, it will go into retry

(hiccup) mode. The retry cycle will always have two dummy

time-outs, plus whatever fraction of the real soft-start time

passes before the detection and shut-off; at that point, the

logic immediately starts a new two dummy cycle time-out.

Both OCP and UVP protect against shorts to GND, but the

responses (and recovery from) are different, as shown in

Table 2. For some combinations of output components and

shorting method, it may be difficult to predict which

protection will trip first (output voltage going too low, or

current going too high). The ISL6341C removes that

uncertainty by disabling the UVP, and relying only on the

OCP. Note that for the other 3 versions, if OCP trips first, it

locks out the UVP from also tripping, so that only the OCP

response (and recovery) are active.

OVERCURRENT EQUATIONS

For all the ISL6341x, versions, the overcurrent function will

trip at a peak inductor current (I

PEAK)

determined by

Equation 1:

where I

OCSET

is the internal OCSET current source (10µA

typical). The OC trip point varies in a system mainly due to

the MOSFET’s r

DS(ON)

variations (over process, current and

temperature). To avoid overcurrent tripping in the normal

operating load range, find the R

OCSET

resistor from

Equation 1 with:

1. The maximum r

DS(ON)

at the highest junction

temperature.

2. The minimum I

OCSET

from the “Electrical Specification

Table” on page 5.

3. Determine I

PEAK

for

where ΔI is the output inductor ripple current.

For an equation for the ripple current see “Output Inductor

Selection” on page 15.

The range of allowable voltages detected (I

OCSET

)

is 0mV to 550mV; but the practical range for typical

MOSFETs is smaller. If the voltage drop across R

OCSET

set too low (< ~20mV), that can cause almost continuous

OCP tripping. It would also be very sensitive to system noise

and in-rush current spikes, so it should be avoided. The

maximum setting is 550mV, but most of the recommended

MOSFETs for the ISL6341x are not expected to handle the

power of the maximum trip point.

There is no way to disable the OCP, but setting it above the

maximum value (>600mV) will come close; for most cases, it

should be high enough (compared to the normal expected

range) to appear disabled. No resistor at all could give the

clamped maximum value (unless the loading on the LGATE

prevents charging the node fully). But there is no low-voltage

clamp on LGATE, so it could rise to over 3V and turn-on for

FIGURE 5. OCP TIMING (ISL6341A, ISL6341C)

UGATE (24V/DIV)

0A>

GND>

INDUCTOR

(10A/DIV)

LGATE (12V/DIV)

GND>

FIGURE 6. OCP RETRY OPERATION (ISL6341A, ISL6341C)

4.8ms4.8ms 0ms TO 4.8ms

4.8ms

OUT

(0.5V/DIV)

GND>

INTERNAL SOFT-START RAMP DELAYS

PEAK

OCSET

DS ON()

-------------------------------------------------=

(EQ. 1)

PEAK

OUT MAX()

ΔI()

----------

ISL6341, ISL6341A, ISL6341B, ISL6341C

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

ISL6341CCRZ-T

Mfr. #:

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Manufacturer:

Renesas / Intersil

Description:

Switching Controllers 10LD 3X3 SYNCH PWM BUCK CONT 5V OR 12V

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