22
LTC1968
1968f
not zero at 0V, but rather at one half its reference, so both
an output offset and a gain error will result. These errors
will vary from part to part, but with a specific LTC1968 and
LTC2420 combination, the errors will be fixed, varying less
than ±0.05% over temperature. So a system that has digi-
tal calibration can be quite accurate despite the nominal
gain and offset error. With 20 bits of resolution, this part
is more accurate than the LTC1968, but the extra resolu-
tion is helpful because it reduces nonlinearity at the LSB
transitions as a digital gain correction is made. Further-
more, its small size and ease of use make it attractive.
This connection is shown in Figure 21b, where the LTC2420
is set to continuously convert by grounding the CS pin. The
gain error will be less if CS is driven at a slower rate,
however, the rate should either be consistent or at a rate
low enough that the LTC1968 and its output capacitor have
fully settled by the beginning of each conversion, so that
the loading errors are consistent.
Other types of ADCs sample the input signal once and
perform a conversion on that one sample. With these
ADCs (Nyquist ADCs), a post filter will be needed in most
cases to reduce the peak error with low input frequencies.
The DC-accurate filter of Figure 13 is attractive from an
error standpoint, but it increases the impedance at the ADC
input. In most cases, the buffered post filter of Figure 12
will be more appropriate for use with Nyquist analog-to-
digital converters.
SYSTEM CALIBRATION
The LTC1968 static accuracy can be improved with end-
system calibration. Traditionally, calibration has been
done at the factory, or at a service depot only, typically
using manually adjusted potentiometers. Increasingly,
systems are being designed for electronic calibration
where the accuracy corrections are implemented in digital
code wherever possible, and with calibration DACs where
necessary. Additionally, many systems are now designed
for self calibration, in which the calibration occurs inside
the machine, automatically without user intervention.
Whatever calibration scheme is used, the linearity of the
LTC1968 will improve the calibrated accuracy over that
achievable with older log/antilog RMS-to-DC converters.
Additionally, calibration using DC reference voltages are
essentially as accurate with the LTC1968 as those using
AC reference voltages. Older log/antilog RMS-to-DC con-
verters required nonlinear input stages (rectifiers) whose
linearity would typically render DC-based calibration
unworkable.
The following are four suggested calibration methods.
Implementations of the suggested adjustments are de-
pendent on the system design, but in many cases, gain and
output offset can be corrected in the digital domain, and
will include the effect of all gains and offsets from the
LTC1968 output through the ADC. Input offset voltage, on
the other hand, will have to be corrected with adjustment
to the actual analog input to the LTC1968.
AC-Only, 1 Point
The dominant error at full scale will be caused by the gain
error, and by applying a full-scale sine wave input, this
error can be measured and corrected for. Unlike older log/
antilog RMS-to-DC converters, the correction should be
made for zero error at full scale to minimize errors through-
out the dynamic range.
The best frequency for the calibration signal is roughly ten
times the –0.1% DC error frequency. For 10µF, –0.1% DC
error occurs at 6Hz, so 60Hz is a good calibration frequency,
although anywhere from 60Hz to 100Hz should suffice.
APPLICATIO S I FOR ATIO
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Figure 21a. Interfacing to DVM/DPM ADC
Figure 21b. Interfacing to LTC2420
C
AVE
LTC1968
OUTPUT
OUT RTN
7106 TYPE
IN HI
IN LO
5
6
31
1968 F21a
30
C
AVE
LTC1968
OUTPUT
OUT RTN
LTC2420
V
IN
SERIAL
DATA
DIGITALLY CORRECT
LOADING ERRORS
GND
SDO
SCK
CS
5
6
3
1968 F21b
4
23
LTC1968
1968f
The trade-off here is that on the one hand, the DC error is
input frequency dependent, so a calibration signal fre-
quency high enough to make the DC error negligible
should be used. On the other hand, as low a frequency as
can be used is best to avoid attenuation of the calibrated
AC signal, either from parasitic RC loading or insufficient
op amp gain. For instance, with a 1kHz calibration signal,
a 1MHz op amp will typically only have 60dB of open-loop
gain, so it could attenuate the calibration signal a full 0.1%.
AC-Only, 2 Point
The next most significant error for AC-coupled applica-
tions will be the effect of output offset voltage, noticeable
at the bottom end of the input scale. This too can be
calibrated out if two measurements are made, one with a
full-scale sine wave input and a second with a sine wave
input (of the same frequency) at 10% of full scale. The
trade-off in selecting this second level is that it should be
small enough that the gain error effect becomes small
compared to the gain error effect at full scale, while on the
other hand, not using so small an input that the input offset
voltage becomes an issue.
The calculations of the error terms for a 200mV full-scale
case are:
Gain =
Reading at 200mV Reading at 20mV
180mV
Output Offset =
Reading at 20mV
Gain
–20mV
DC, 2 Point
DC-based calibration is preferable in many cases because
a DC voltage of known, good accuracy is easier to gener-
ate than such an AC calibration voltage. The only down
side is that the LTC1968 input offset voltage plays a role.
It is therefore suggested that a DC-based calibration
scheme check at least two points: ±full scale. Applying the
–full-scale input can be done by physically inverting the
voltage or by applying the same +full-scale input to the
opposite LTC1968 input.
For an otherwise AC-coupled application, only the gain
term may be worth correcting for, but for DC-coupled
applications, the input offset voltage can also be calcu-
lated and corrected for.
The calculations of the error terms for a 200mV full-scale
case are:
Gain =
Reading at 200mV + Reading at – 200mV
400mV
Input Offset =
Reading at 200mV Reading at 200mV
2Gain
Note: Calculation of and correction for input offset voltage
are the only way in which the two LTC1968 inputs (IN1,
IN2) are distinguishable from each other. The calculation
above assumes the standard definition of offset; that a
positive offset is the case of a positive voltage error inside
the device that must be corrected by applying a like
negative voltage outside. The offset is referred to which-
ever pin is driven positive for the +full-scale reading.
DC, 3 Point
One more point is needed with a DC calibration scheme to
determine output offset voltage: +10% of full scale.
The calculation of the input offset is the same as for the
2-point calibration above, while the gain and output offset
are calculated for a 200mV full-scale case as:
Gain =
Reading at 200mV Reading at 20mV
180mV
Output Offset =
Reading at 200mV +Reading at 200mV – 400mV • Gain
2
APPLICATIO S I FOR ATIO
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LTC1968
1968f
APPLICATIO S I FOR ATIO
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TROUBLESHOOTING GUIDE
Top Ten LTC1968 Application Mistakes
1. Circuit won’t work–Dead On Arrival–no power drawn.
Probably forgot to enable the LTC1968 by pulling
Pin 8 low.
Solution: Tie Pin 8 to Pin 1.
2. Circuit won’t work, but draws power. Zero or very
little output, single-ended input application.
Probably didn’t connect both input pins.
Solution: Tie both inputs to something. See “Input
Connections” in the Design Cookbook.
4. Gain is low by a few percent, along with other screwy
results.
Probably tried to use output in a floating, differential
manner.
Solution: Tie Pin 6 to a low impedance. See “Output
Connections” in the Design Cookbook.
LTC1968
CONNECT PIN 3
IN1
2
3
NC
IN2
1968TS02
LTC1968
IN1
2
3
IN2
1968 TS03
DC-COUPLE ONE INPUT
LTC1968
DC-CONNECT ONE INPUT
IN1
2
3
IN2
3. Screwy results, particularly with respect to linearity
or high crest factors; differential input application.
Probably AC-coupled both input pins.
Solution: Make at least one input DC-coupled. See
“Input Connections” in the Design Cookbook.
TYPE 7136
ADC
LTC1968
HI
31
30
5
6
LO
V
OUT
OUT RTN
1968 TS04
GROUND PIN 6
5. Offsets perceived to be out of specification because 0V
in 0V out.
The offsets are not specified at 0V in. No RMS-to-
DC converter works well at 0 due to a divide-by-zero
calculation.
Solution: Measure V
IOS
/V
OOS
by extrapolating read-
ings > ±5mV
DC
.
6. Linearity perceived to be out of specification particu-
larly with small input signals.
This could again be due to using 0V in as one of the
measurement points.
Solution: Check Linearity from 5mV
RMS
to
500mV
RMS
.
The input offset voltage can cause small AC linear
ityerrors at low input amplitudes as well. See “Error
Analyses” section.
Possible Solution: Include a trim for input offset.

LTC1968IMS8#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Management Specialized - PMIC Prec Wide B&width, RMS-to-DC Conv
Lifecycle:
New from this manufacturer.
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