9
LTC1968
1968f
APPLICATIO S I FOR ATIO
WUUU
Note that the internal scalings are such that the ∆Σ output
duty cycle is limited to 0% or 100% only when V
IN
exceeds
±4 • V
OUT
.
Linearity of an RMS-to-DC Converter
Linearity may seem like an odd property for a device that
implements a function that includes two very nonlinear
processes: squaring and square rooting.
However, an RMS-to-DC converter has a transfer func-
tion, RMS volts in to DC volts out, that should ideally have
a 1:1 transfer function. To the extent that the input to
output transfer function does not lie on a straight line, the
part is nonlinear.
A more complete look at linearity uses the simple model
shown in Figure 5. Here an ideal RMS core is corrupted by
both input circuitry and output circuitry that have imper-
fect transfer functions. As noted, input offset is introduced
in the input circuitry, while output offset is introduced in
the output circuitry.
Any nonlinearity that occurs in the output circuity will
corrupt the RMS in to DC out transfer function. A nonlin-
earity in the input circuitry will typically corrupt that
transfer function far less simply because with an AC input,
the RMS-to-DC conversion will average the nonlinearity
from a whole range of input values together.
But the input nonlinearity will still cause problems in an
RMS-to-DC converter because it will corrupt the accuracy
as the input signal shape changes. Although an RMS-to-
DC converter will convert any input waveform to a DC
output, the accuracy is not necessarily as good for all
waveforms as it is with sine waves. A common way to
describe dynamic signal wave shapes is Crest Factor. The
crest factor is the ratio of the peak value relative to the RMS
value of a waveform. A signal with a crest factor of 4, for
instance, has a peak that is four times its RMS value.
The ∆Σ modulator has a single-bit output whose average
duty cycle (D) will be proportional to the ratio of the input
signal divided by the output. The ∆Σ is a 2nd order
modulator with excellent linearity. The single-bit output is
used to selectively buffer or invert the input signal. Again,
this is a circuit with excellent linearity, because it operates
at only two points: ±1 gain; the average effective multipli-
cation over time will be on the straight line between these
two points. The combination of these two elements again
creates a lowpass filter input signal equal to (V
IN
)
2
/V
OUT
,
which, as shown above, results in RMS-to-DC conversion.
The lowpass filter performs the averaging of the RMS
function and must be a lower corner frequency than the
lowest frequency of interest. For line frequency measure-
ments, this filter is simply too large to implement on-chip,
but the LTC1968 needs only one capacitor on the output
to implement the lowpass filter. The user can select this
capacitor depending on frequency range and settling time
requirements, as will be covered in the Design Cookbook
section to follow.
This topology is inherently more stable and linear than log/
antilog implementations primarily because all of the signal
processing occurs in circuits with high gain op amps
operating closed loop.
More detail of the LTC1968 inner workings is shown in the
Simplified Schematic towards the end of this data sheet.
Figure 4. Topology of LTC1968
∆-Σ
REF
V
IN
V
OUT
LPF
1968 F04
±1
D
V
V
IN
OUT
α
INPUT CIRCUITRY
• V
IOS
• INPUT NONLINEARITY
IDEAL
RMS-TO-DC
CONVERTER
OUTPUT CIRCUITRY
• V
OOS
• OUTPUT NONLINEARITY
INPUT OUTPUT
1968 F05
Figure 5. Linearity Model of an RMS-to-DC Converter
