ADF4157 Data Sheet
Rev. D | Page 14 of 24
R DIVIDER REGISTER (R2) MAP
With R2[2:0] set to 010, the on-chip R divider register is
programmed as shown in Figure 19.
CSR Enable
Setting this bit to 1 enables cycle slip reduction. This is a
method for improving lock times. Note that the signal at the PFD
must have a 50% duty cycle for cycle slip reduction to work. In
addition, the charge pump current setting must be set to a
minimum. See the Cycle Slip Reduction for Faster Lock Times
section for more information.
Note also that the cycle slip reduction feature can only be
operated when the phase detector polarity setting is positive
(DB6 in Register 3). It cannot be used if the phase detector
polarity is set to negative.
Charge Pump Current Setting
Bits DB[27:24] set the charge pump current setting. This should
be set to the charge pump current that the loop filter is designed
with (see Figure 19).
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with INT, FRAC,
and MOD, determine the overall division ratio from RF
IN
x to
the PFD input.
Operating at CML levels, it takes the clock from the RF input
stage and divides it down for the counters. It is based on
a synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 3 GHz. Therefore, when operating
the ADF4157 above 3 GHz, the prescaler must be set to 8/9.
The prescaler limits the INT value.
With P = 4/5, N
MIN
= 23.
With P = 8/9, N
MIN
= 75.
RDIV2
Setting this bit to 1 inserts a divide-by-2 toggle flip-flop
between the R counter and the PFD. This can be used to
provide a 50% duty cycle signal at the PFD for use with cycle
slip reduction.
Reference Doubler
Setting DB[20] to 0 feeds the REF
IN
signal directly to the 5-bit
RF R counter, disabling the doubler. Setting this bit to 1 multiplies
the REF
IN
frequency by a factor of 2 before feeding into the 5-bit
R counter. When the doubler is disabled, the REF
IN
falling edge
is the active edge at the PFD input to the fractional synthesizer.
When the doubler is enabled, both the rising edge and falling
edge of REF
IN
become active edges at the PFD input.
The maximum allowed REF
IN
frequency when the doubler is
enabled is 30 MHz.
5-Bit R Counter
The 5-bit R counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the phase frequency detector (PFD). Division ratios from
1 to 32 are allowed.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
