ADF4157 Data Sheet
Rev. D | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CP
CPGND
AGND
AV
DD
RF
IN
A
RF
IN
B
R
SET
DV
DD
MUXOUT
LE
CE
REF
IN
DGND
CLK
DATA
V
P
ADF4157
TOP VIEW
(Not to Scale)
05874-003
Figure 3. TSSOP Pin Configuration
5874-004
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE THERMALLY CONNECTED TO A COPPER
PLANE FOR ENHANCED THERMAL PERFORMANCE.
THIS PAD SHOULD BE CONNECTED TO AGND.
14
13
12
1
3
4
LE
15 MUXOUT
DATA
CLK
11
CE
CPGND
AGND
2
AGND
RF
IN
B
5
RF
IN
A
7
AV
DD
6
AV
DD
8
REF
IN
9
DGND
10
D
GND
19
R
SET
20
CP
18 V
P
17 DV
DD
16
D
V
DD
ADF4157
TOP VIEW
(Not to Scale)
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic Description
1 19 R
SET
Connecting a resistor between this pin and ground sets the maximum charge pump output
current.
The relationship between I
CP
and R
SET
is
SET
CPMAX
R
I
5.25
where:
R
SET
= 5.1 kΩ.
I
CPMAX
= 5 mA.
2 20 CP
Charge Pump Output. When enabled, this pin provides ±I
CP
to the external loop filter, which, in
turn, drives the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RF
IN
B
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane
with a small bypass capacitor, typically 100 pF.
6 5 RF
IN
A Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7 6, 7 AV
DD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. AV
DD
has a value of 3 V ± 10%. AV
DD
must have
the same voltage as DV
DD
.
8 8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent
input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it
can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output
into three-state mode.
11 12 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the input shift register on the CLK rising edge. This input is a high impedance
CMOS input.
12 13 DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
This input is a high impedance CMOS input.
13 14 LE
Load Enable, CMOS Input. When LE is high, the data stored in the input shift register is loaded
into one of the five latches, with the latch selected using the control bits.
14 15 MUXOUT
This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
