82V3012PVG8 Datasheet 82V3012PVG, 82V3012PVG8 | P10-P12

Functional Description 10 February 6, 2009

IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

2 FUNCTIONAL DESCRIPTION

The IDT82V3012 is a T1/E1/OC3 WAN PLL with dual reference

inputs, providing timing (clock) and synchronization (framing) signals to

interface circuits for multitrunk T1/E1 and STS3/OC3 links. The details

are described in the following sections.

2.1 STATE CONTROL CIRCUIT

The State Control Circuit is an important part in the IDT82V3012. It is

used to control the TIE block and the DPLL block as shown in Figure - 2.

The control is based on the result of Invalid Input Signal Detection and

the logic levels on the MODE_sel0, MODE_sel1, IN_sel and TIE_en

pins.

The IDT82V3012 can be operated in three different modes: Normal,

Holdover and Freerun. The operating mode is selected by the

MODE_sel1 and MODE_sel0 pins, as shown in Table - 1.

Figure - 3 shows the state control diagram. All state changes occur

synchronously on the rising edge of F8o. Three operating modes,

Normal (S1), Holdover (S3) and Freerun (S0) can be switched from one

to another by changing the logic levels on the MODE_sel0 and

MODE_sel1 pins.

Figure - 2 State Control Circuit

Figure - 3 State Control Diagram

Table - 1 Operating Modes Selection

Mode Selection Pins

Operating Mode

MODE_sel1 MODE_sel0

00 Normal

0 1 Holdover

1 0 Freerun

11 Reserved

State Control Circuit

MODE_sel1 MODE_sel0TIE_en

Output of the

Invalid Input

Signal Detection

F8o

TIE Block

Enable/Disable

DPLL Block

Mode Control

IN_sel

Normal

Mode_sel1 = 0

Mode_sel0 = 0

Holdover

Mode_sel1 = 0

Mode_sel0 = 1

Freerun

Mode_sel1 = 1

Mode_sel0 = 0

(Invalid Input Reference Signal)

(Valid Input Reference Signal)

TIE Enable (TIE_en = H)

(

n =

)

Reset *

Short Time Holdover

Mode_sel1 = 0

Mode_sel0 = 0

)

E D

(

)

Auto - Holdover

Mode_sel1 = 0

Mode_sel0 = 0

* Note: After reset, the Mode_sel1 and Mode_sel0 should be initially set to '10' or '00'.

Auto TIE Disable

(Valid Input Reference Signal)

TIE Disable (TIE_en = L)

Functional Description 11 February 6, 2009

IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

The mode changes between Normal (S1) and Auto-Holdover (S2)

are triggered by the Invalid Input Reference Detection Circuit and are

irrelative to the logic levels on the MODE_sel0 and MODE_sel1 pins. At

the stage of S1, if the input reference is invalid (out of the capture

range), the operating mode will be changed to Auto-Holdover (S2)

automatically. At the stage of S2, if no IN_sel transient occurs and the

input reference becomes valid, the operating mode will be changed back

to Normal (S1) automatically. If an IN_sel transient is detected at the

stage of S2, the operating mode will be changed to Short Time Holdover

(S4) with the TIE Control Block automatically disabled. Refer to “2.5

Invalid Input Signal Detection” for more information.

The mode changes between Normal (S1) and Short Time Holdover

(S4) are triggered by the IN_sel transient. At the stage of S1, if a voltage

transient occurs on the IN_sel pin, the operating mode will be changed

to Short Time Holdover (S4) automatically. At the stage of S4, if no

voltage transient occurs on the IN_sel pin, the operating mode will be

changed back to S1 automatically. See “2.3 Reference Input Switch” for

details.

When the operating mode is changed from one to another, the TIE

control block is automatically disabled as shown in Figure - 3, except the

changes from Short Time Holdover (S4), Holdover (S3) or Auto-

Holdover (S2) to Normal (S1). In the case of changing from S4, S3 or S2

to S1, the TIE control block is enabled or disabled by the TIE_en pin.

2.1.1 NORMAL MODE

The Normal mode is typically used when a slave clock source

synchronized to the network is required.

In this mode, the IDT82V3012 provides timing (C1.5o, C3o, C2o,

C4o, C8o, C16o, C19o, C32o) and synchronization (F0o, F8o, F16o,

F19o, F32o, TSP, RSP) signals. All these signals are synchronous to

one of the two input references. The nominal frequency of the input

reference can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz.

After reset, the IDT82V3012 will take 30 seconds at most to make

the output signals synchronous (phase locked) to the input reference.

Whenever the IDT82V3012 works in the Normal mode, the NORMAL

pin will be set to logic high.

2.1.2 FAST LOCK MODE

The Fast Lock mode is a submode of the Normal mode. It allows the

DPLL to lock to a reference more quickly than the Normal mode allows.

Typically, the locking time in the Fast Lock mode is less than 500 ms.

When the FLOCK pin is set to high, the Fast Lock mode will be

enabled.

2.1.3 HOLDOVER MODE

The Holdover mode is typically used for short duration (e.g., 2

seconds) while network synchronization is temporarily disrupted.

In the Holdover mode, the IDT82V3012 provides timing and

synchronization signals that are not locked to an external reference

signal, but are based on storage techniques. In the Normal mode, when

the output frequency is locked to the input reference signal, a numerical

value corresponding to the output frequency is stored alternately in two

memory locations every 30 ms. When the device is changed to the

Holdover mode, the stored value from between 30 ms and 60 ms is used

to set the output frequency of the device.

The frequency accuracy in the Holdover mode is ±0.025 ppm, which

corresponds to a worst case of 18 frame (125 µs per frame) slips in 24

hours. This meets the AT&T TR62411 and Telcordia GR-1244-CORE

Stratum 3 requirement of ±0.37 ppm (255 frame slips per 24 hours).

Whenever the IDT82V3012 works in the Holdover mode, the

HOLDOVER pin will be set to logic high.

2.1.4 FREERUN MODE

The Freerun mode is typically used when a master clock source is

required, or used when a system is just powered up and the network

synchronization has not been achieved.

In this mode, the IDT82V3012 provides timing and synchronization

signals which are based on the master clock frequency (OSCi) only, and

are not synchronized to the input reference signal.

The accuracy of the output clock is equal to the accuracy of the

master clock (OSCi). So if a ±32 ppm output clock is required, the

master clock must also be ±32 ppm. Refer to “2.8 OSC” for more

information.

Whenever the IDT82V3012 works in the Freerun mode, the

FREERUN pin will be set to logic high.

2.2 FREQUENCY SELECT CIRCUIT

The input reference can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44

MHz. The F0_sel1 and F0_sel0 pins select one of the four frequencies

for the reference input 0 (Fref0). The F1_sel1 and F1_sel0 pins select

one of the four frequencies for the reference input 1 (Fref1). See Table -

2 and Table - 3 for details.

The reference inputs Fref0 and Fref1 may have different frequencies

applied to them. Every time the frequency is changed, the device must

be reset to make the change effective.

2.3 REFERENCE INPUT SWITCH

The IDT82V3012 accepts two simultaneous reference signals Fref0

and Fref1, and operates on the falling edge (8 kHZ, 1.544 MHz and

2.048 MHz) or rising edge (19.44 MHz). One of the two reference

signals will be input to the device, as determined by the IN_sel pin. See

Table - 2 Fref0 Frequency Selection

Frequency Selection Pins

Fref0 Input Frequency

F0_sel1 F0_sel0

0 0 19.44 MHz

01 8 kHz

1 0 1.544 MHz

1 1 2.048 MHz

Table - 3 Fref1 Frequency Selection

Frequency Selection Pins

Fref1 Input Frequency

F1_sel1 F1_sel0

0 0 19.44 MHz

01 8 kHz

1 0 1.544 MHz

1 1 2.048 MHz

Functional Description 12 February 6, 2009

IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

Table - 4. The selected reference signal is sent to the TIE control block,

Reference Input Monitor and Invalid Input Signal Detection block for

further processing.

When a transient voltage occurs on the IN_sel pin, the operating

mode will be changed to Short Time Holdover (S4) with the TIE Control

Block automatically disabled. At the stage of S4, if no IN_sel transient

occurs, the reference signal will be switched from one to the other, and

the operating mode will be changed back to Normal (S1) automatically.

During the change from S4 to S1, the TIE Control Block can be enabled

or disabled, depending on the logic level on the TIE_en pin. See Figure -

3 for details.

2.4 REFERENCE INPUT MONITOR

The Telcordia GR-1244-CORE standard recommends that the DPLL

should be able to reject the references that are off the nominal frequency

by more than ±12 ppm. The IDT82V3012 monitors the Fref0 and Fref1

frequencies and outputs two signals at MON_out0 pin and MON_out1

pin to indicate the monitoring results respectively. Whenever the Fref0

frequency is off the nominal frequency by more than ±12 ppm, the

MON_out0 pin will go high. The MON_out1 pin indicates the monitoring

result of Fref1 in the same way. The MON_out0 and MON_out1 signals

are updated every 2 seconds.

2.5 INVALID INPUT SIGNAL DETECTION

This circuit is used to detect if the selected input reference (Fref0 or

Fref1) is out of the capture range. Refer to “3.6 Capture Range” for

details. This includes a complete loss of the input reference and a large

frequency shift in the input reference.

If the input reference is invalid (out of the capture range), the

IDT82V3012 will be automatically changed to the Holdover mode (Auto-

Holdover). When the input reference becomes valid, the device will be

changed back to the Normal mode and the output signals will be locked

to the input reference.

In the Holdover mode, the output signals are based on the output

reference signal 30 ms to 60 ms prior to entering the Holdover mode.

The amount of phase drift while in holdover can be negligible because

the Holdover mode is very accurate (e.g., 0.025 ppm). Consequently,

the phase delay between the input and output after switching back to the

Normal mode is preserved.

2.6 TIE CONTROL BLOCK

If the current reference is badly damaged or lost, it is necessary to

use the other reference or the one generated by storage techniques

instead. But when switching the reference, a step change in phase on

the input reference will occur. A step change in phase in the input to

DPLL may lead to an unacceptable phase change on the output signals.

The TIE control block, when enabled, prevents a step change in phase

on the input reference signals from causing a step change in phase on

the output of the DPLL block. Figure - 4 shows the TIE Control Block

diagram.

Figure - 4 TIE Control Block Diagram

When the TIE Control Block is enabled manually or automatically (by

the TIE_en pin or TIE auto-enable logic generated by the State Control

Circuit), it works under the control of the Step Generation circuit.

At the Measure Circuit stage, the selected reference signal (Fref0 or

Fref1) is compared with the feedback signal (current output feed back

from the Frequency Select Circuit). The phase difference between the

input reference and the feedback signal is stored in the Storage Circuit

for TIE correction. According to the value stored in the storage circuit,

the Trigger Circuit generates a virtual reference with the same phase as

the previous reference. In this way, the reference can be switched

without generating a step change in phase.

Figure - 5 shows the phase transient that will result if a reference

switch is performed with the TIE Control Block enabled.

The value of the phase difference in the Storage Circuit can be

cleared by applying a logic low reset signal to the TCLR pin. The

minimum width of the reset pulse should be 300 ns.

When the IDT82V3012 primarily enters the Holdover mode for a

short time period and then returns back to the Normal mode, the TIE

Control Circuit should not be enabled. This will prevent undesired

accumulated phase change between the input and output.

If the TIE Control Block is disabled manually or automatically, a

reference switch will result in a phase alignment between the input

signal and the output signal as shown in Figure - 6. The slope of the

phase adjustment is limited to 5 ns per 125 µs.

Table - 4 Input Reference Selection

IN_sel Input Reference

0Fref0

1Fref1

Step Generation

TIE_en

Reference

Select Circuit

Fref0

Fref1

IN_sel

Measure

Circuit

Storage

Circuit

Trigger

Circuit

Feedback

Signal

TCLR

Fref

Virtual

Reference

Signal

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

82V3012PVG8

Mfr. #:

Buy 82V3012PVG8

Manufacturer:

IDT

Description:

Clock Generators & Support Products 3.3V T1/E1/19.44M Stratum dual ref WAN

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

82V3012PVG8

82V3012PVG8

Products related to this Datasheet