Timing Characteristics 28 February 6, 2009
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
t
C19D
F8o to C19o delay -8 0 +8 ns
t
C32D
F8o to C32o delay -2 2 +2 ns
t
TSPD
F8o to TSP delay -3 0 +3 ns
t
RSPD
F8o to RSP delay -3 0 +3 ns
t
C15W
C1.5o pulse width high or low 323 ns
t
C3W
C3o pulse width high or low 161 ns
t
C6W
C6o pulse width high or low 82 ns
t
C2W
C2o pulse width high or low 244 ns
t
C4W
C4o pulse width high or low 122 ns
t
C8W
C8o pulse width high or low 61 ns
t
C16W
C16o pulse width high or low 30.5 ns
t
C19W
C19o pulse width high or low 25 ns
t
C32WH
C32o pulse width high 14.4 ns
t
TSPW
TSP pulse width high 486 ns
t
RSPW
RSP pulse width high 490 ns
t
F0WL
F0o pulse width low 243 ns
t
F8WH
F8o pulse width high 123.6 ns
t
F16WL
F16o pulse width low 60.9 ns
t
F19WH
F19o pulse width high 25 ns
t
0RF
Output clock and frame pulse rise or fall time 3 ns
t
S
Input controls setup Time 100 ns
t
H
Input controls hold Time 100 ns
t
F16D
F8o to F16o delay 27.1 30.1 33.1 ns
t
F19D
F8o to F19o delay 17 25 33 ns
t
F32D
F8o to F32o delay 12 15.8 19 ns
t
F32S
F32o setup to C32o falling 11 ns
t
F32H
F32o hold to C32o falling 11 ns
t
F32WL
F32o pulse width low 30.6 ns
Parameter Description Min. Typ. Max. Units Test Conditions
