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82V3012PVG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
AC Electrical Characteristics 25 February 6, 2009
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
7.12 2.048 MHZ INPUT JITTER TOLERANCE
7.13 19.44 MHZ INPUT JITTER TOLERANCE
Description Min. Typ. Max. Units
Test Conditions / Notes
(see “Notes” on page 26)
Jitter tolerance for 1 Hz input
150 UIpp 1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 5 Hz input 140 UIpp 1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 20 Hz input 130 UIpp 1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 300 Hz input 40 UIpp 1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 400 Hz input 33 UIpp 1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 700 Hz input 18 UIpp 1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 2400 Hz input 5.5 UIpp 1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 10 kHz input 1.3 UIpp 1-3, 8, 10-15, 22-23, 25-27, 31
Jitter tolerance for 100 kHz input 0.4 UIpp 1-3, 8, 10-15, 22-23, 25-27, 31
Description Min. Typ. Max. Units
Test Conditions / Notes
(see “Notes” on page 26)
Jitter tolerance for 12 µHz input
2800 UIpp 1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 178 µHz input 2800 UIpp 1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 0.0016 Hz input 311 UIpp 1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 0.0156 Hz input 311 UIpp 1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 0.125 Hz input 39 UIpp 1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 19.3 Hz input 39 UIpp 1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 500 Hz input 1.5 UIpp 1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 6.5 kHz input 1.5 UIpp 1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 65 kHz input 0.15 UIpp 1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 1.3 MHz input 0.15 UIpp 1-3, 9-15, 22-23, 25-27, 37
AC Electrical Characteristics 26 February 6, 2009
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
Notes:
Voltages are with respect to ground (V
SS
) unless otherwise stated. Supply voltage and
operating temperature are as per Recommended Operating Conditions. Timing
parameters are as per Timing Parameter Measurement Voltage Levels.
1. Fref0 reference input selected.
2. Fref1 reference input selected.
3. Normal mode selected.
4. Holdover mode selected.
5. Freerun mode selected.
6. 8 kHz frequency mode selected.
7. 1.544 MHz frequency mode selected.
8. 2.048 MHz frequency mode selected.
9. 19.44 MHz frequency mode selected.
10. Master clock input OSCi at 20 MHz ±0 ppm.
11. Master clock input OSCi at 20 MHz ±32 ppm.
12. Master clock input OSCi at 20 MHz ±100 ppm.
13. Selected reference input at ±0 ppm.
14. Selected reference input at ±32 ppm.
15. Selected reference input at ±100 ppm.
16. For Freerun mode of ±0 ppm.
17. For Freerun mode of ±32 ppm.
18. For Freerun mode of ±100 ppm.
19. For capture range of ±230 ppm.
20. For capture range of ±198 ppm.
21. For capture range of ±130 ppm.
22. 25 pF capacitive load.
23. OSCi Master Clock jitter is less than 2 nspp, or 0.04 UIpp where 1 UIpp = 1/20 MHz.
24. Jitter on reference input is less than 7 nspp.
25. Applied jitter is sinusoidal.
26. Minimum applied input jitter magnitude to regain synchronization.
27. Loss of synchronization is obtained at slightly higher input jitter amplitudes.
28. Within 10 ms of the state, reference or input change.
29. 1 UIpp = 125 µs for 8 kHz signals.
30. 1 UIpp = 648 ns for 1.544 MHz signals.
31. 1 UIpp = 488 ns for 2.048 MHz signals.
32. 1 UIpp = 323 ns for 3.088 MHz signals.
33. 1 UIpp = 244 ns for 4.096 MHz signals.
34. 1 UIpp = 158 ns for 6.312 MHz signals.
35. 1 UIpp = 122 ns for 8.192 MHz signals.
36. 1 UIpp = 61 ns for 16.484 MHz signals.
37. 1 UIpp = 51 ns for 19.44 MHz signals.
38. 1 UIpp = 30 ns for 32.968 MHz signals.
39. No filter.
40. 40 Hz to 100 kHz bandpass filter.
41. With respect to reference input signal frequency.
42. After a
RST or TCLR.
43. Master clock duty 40% to 60%.
44. Prior to Holdover mode, device as in Normal mode and phase locked.
45. With input frequency offset of 100 ppm.
Timing Characteristics 27 February 6, 2009
IDT82V3012 T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
8 TIMING CHARACTERISTICS
8.1 TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS
Figure - 11 Timing Parameter Measurement Voltage Levels
Notes:
1. Voltages are with respect to ground (VSS) unless otherwise stated.
2. Supply voltage and operating temperature are as per Recommended Operating Conditions.
3. Timing for input and output signals is based on the worst case result of the CMOS thresholds.
8.2 INPUT/OUTPUT TIMING
Parameter Description CMOS Units
V
T
Threshold Voltage
0.5V
DDD
V
V
HM
Rise and Fall Threshold Voltage High
0.7V
DDD
V
V
LM
Rise and Fall Threshold Voltage Low
0.3V
DDD
V
Parameter Description Min. Typ. Max. Units Test Conditions
t
RW
Reference input pulse width high or low
51 ns
8 kHz, 1.544 MHz or 2.048 MHz
reference input
5 ns 19.44 MHz reference input
t
IRF
Reference input rise or fall time 10 ns
t
R8D
8 kHz reference input to F8o delay 8 ns
t
R15D
1.544 MHz reference input to F8o delay 332 ns
t
R2D
2.048 MHz reference input to F8o delay 253 ns
t
R19D
19.44 MHz reference input to F8o delay 8 ns
t
F0D
F8o to F0o delay 118 121 124 ns
t
F16S
F16o setup to C16o falling 25 40 ns
t
F16H
F16o hold to C16o falling 25 40 ns
t
F19S
F19o setup to C19o falling 20 35 ns
t
F19H
F19o hold to C19o falling 20 35 ns
t
C15D
F8o to C1.5o delay -3 0 +3 ns
t
C3D
F8o to C3o delay -3 1.6 +3 ns
t
C6D
F8o to C6o delay -3 1.6 +3 ns
t
C2D
F8o to C2o -2 0 +2 ns
t
C4D
F8o to C4o -2 0 +2 ns
t
C8D
F8o to C8o delay -2 0 +2 ns
t
C16D
F8o to C16o delay -2 0 +2 ns
Timing Reference Points
t
IRF,
t
ORF
t
IRF,
t
ORF
V
HM
V
T
V
LM
All Siganls
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

82V3012PVG8

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Buy 82V3012PVG8
Manufacturer:
IDT
Description:
Clock Generators & Support Products 3.3V T1/E1/19.44M Stratum dual ref WAN
Lifecycle:
New from this manufacturer.
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