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TSL2581FN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134 − MARCH 2011
10
r
r
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
www.taosinc.com
Command Register
The command register specifies the address of the target register for subsequent read and write operations and
contains eight bits as described in Table 3. The command register defaults to 00h at power on.
Table 3. Command Register
6754
ADDRESS
2310
CMD TRANSACTION
Reset
00h
Bit :
FIELD BIT DESCRIPTION
CMD 7 Select command register. Must write as 1 when addressing COMMAND register.
Select type of transaction to follow in subsequent data transfers:
FIELD VALUE DESCRIPTION
00 Repeated byte protocol transaction
TRANSACTION
6:5
01 Auto-increment protocol transaction
TRANSACTION
6
:
5
10 Reserved — Do not use
11 Special function — See description below
Transaction type 00 will repeatedly read the same register with each data access.
Transaction type 01 will provide an auto−increment function to read successive register bytes.
Address field/special function field. Depending on the transaction type, see above, this field either
specifies a special function command or selects the specific control-status-register for following write and
read transactions. The field values listed below apply only to special function commands:
FIELD VALUE DESCRIPTION
00000 Reserved. Write as 0000b.
ADDRESS
40
00001 Clear any pending interrupt and is a write−once−to−clear bit
ADDRESS 4:0
00010
When the Timing Register is set to 00h, a SendByte command with the ADDRESS field
set to 0010b will stop a manual integration. The actual length of the integration cycle
may be read in the MANUAL INTEGRATION TIMER Register.
00011
When the Timing Register is set to 00h, a SendByte command with the ADDRESS field
set to 0011b will start a manual integration. The actual length of the integration cycle
may be read in the MANUAL INTEGRATION TIMER Register.
x11xx Reserved. Write as 11xxb.
NOTE: An I
2
C block transaction will continue until the Master sends a stop condition. Only the Send Byte Protocol should be used when clearing
interrupts.
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134 − MARCH 2011
11
The LUMENOLOGY r Company
r
r
Copyright E 2011, TAOS Inc.
www.taosinc.com
Control Register (00h)
The CONTROL register primarily used to power the TSL258x device up and down as shown in Table 4.
Table 4. Control Register
6754
POWER
2310
Reserved
Resv
ADC_VALID Reserved ADC_ENADC_INTR
Address
00h
Reset
00h
Bit :
FIELD BIT DESCRIPTION
Reserved 7:6 Reserved. Write as 0.
ADC_INTR 5 ADC Interrupt. Read only. Indicates that the device is asserting an interrupt.
ADC_VALID 4 ADC Valid. Read only. Indicates that the ADC channel has completed an integration cycle.
Reserved 3:2 Reserved. Write as 0.
ADC_EN 1
ADC Enable. This field enables the two ADC channels to begin integration. Writing a 1 activates the ADC
channels, and writing a 0 disables the ADCs.
POWER 0 Power On. Writing a 1 powers on the device, and writing a 0 turns it off.
NOTE: ADC_EN and POWER must be asserted before the ADC changes will operate correctly. After POWER is asserted, a 2-ms delay is
required before asserting ADC_EN.
NOTE: The TSL258x device registers should be configured before ADC_EN is asserted.
Timing Register (01h)
The TIMING register controls the internal integration time of the ADC channels in 2.7-ms increments. The
TIMING register defaults to 00h at power on.
Table 5. Timing Register
67542310
ATIME
Address
01h
Reset
00h
Bit :
FIELD BIT DESCRIPTION
Integration Cycles. Specifies the integration time in 2.7-ms intervals. Time is expressed as a 2’s
complement number. So, to quickly work out the correct value to write: (1) determine the number of
2.7-ms intervals required, and (2) then take the 2’s complement. For example, for a 1 × 2.7-ms interval,
0xFF should be written. For 2 × 2.7-ms intervals, 0xFE should be written. The maximum integration time
is 688.5 ms (00000001b).
Writing a 0x00 to this register is a special case and indicates manual timing mode. See CONTROL and
MANUAL INTEGRATION TIMER Registers for other device options related to manual integration.
INTEG_CYCLES TIME VALUE
ATIME
7:0
− Manual integration 00000000
ATIME
7:
0
1 2.7 ms 11111111
2 5.4 ms 11111110
19 51.3 ms 11101101
37 99.9 ms 11011011
74 199.8 ms 10110110
148 399.6 ms 01101100
255 688.5 ms 00000001
NOTE: The Send Byte protocol cannot be used when ATIME is greater than 127 (for example ATIME[7] = 1) since the upper bit is set aside for
write transactions in the COMMAND register.
TSL2581, TSL2583
LIGHT-TO-DIGITAL CONVERTER
TAOS134 − MARCH 2011
12
r
r
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
www.taosinc.com
Interrupt Register (02h)
The INTERRUPT register controls the extensive interrupt capabilities of the device. The open-drain interrupt
pin is active low and requires a pull-up resistor to V
BUS
in order to pull high in the inactive state. The Interrupt
Register provides control over when a meaningful interrupt will occur. The concept of meaningful change can
be defined by the user both in terms of light intensity and time, or persistence of that change in intensity. The
value must cross the threshold (as configured in the Threshold Registers 03h through 06h) and persist for some
period of time, as outlined in Table 8.
When a level Interrupt is selected, an interrupt is generated whenever the last conversion results in a value
outside of the programmed threshold window. The interrupt is active-low and remains asserted until cleared by
writing an 11 in the TRANSACTION field in the COMMAND register.
Note: Interrupts are based on the value of Channel 0 only.
Table 6. Interrupt Control Register
67542310
INTR_STOPResv Resv PERSIST
Address
02h
Reset
00h
Bit :
INTR
FIELD BITS DESCRIPTION
Resv 7 Reserved. Write as 0.
INTR_STOP 6
Stop ADC integration on interrupt. When high, ADC integration will stop once an interrupt is asserted. To
resume operation (1) de-assert ADC_EN using CONTROL register, (2) clear interrupt using COMMAND
register, and (3) re-assert ADC_EN using CONTROL register. Note: Use this bit to isolate a particular
condition when the sensor is continuously integrating.
Resv 5 Reserved. Write as 0.
INTR 4 INTR Control Select. This field determines mode of interrupt logic according to Table 7, below.
PERSIST 3:0 Interrupt persistence. Controls rate of interrupts to the host processor as shown in Table 8, below.
Table 7. Interrupt Control Select
INTR FIELD VALUE READ VALUE
0 Interrupt output disabled
1 Level Interrupt
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

TSL2581FN

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Light to Digital Converters Light to Digital 30x Sensitivity
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