NCP81239MNTXG Datasheet NCP81239MNTXG | P10-P12

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Feedback and Output Voltage Profile

The feedback of the converter output voltage is connected

to the FB pin of the device through a resistor divider.

Internally FB is connected to the inverting input of the

internal transconductance error amplifier. The

non−inverting input of the gm amplifier is connected to the

internal reference. The internal reference voltage is by

default 0.5 V. Therefore a 10:1 resistor divider from the

converter output to the FB will set the output voltage to 5V

in default. The reference voltage can be adjusted with

10 mV(default) or 5 mV steps from 0.1 V to 2.55 V through

the voltage profile register (01H), which makes the

continuous output voltage profile possible through an

external resistor divider. For example, by default, if the

external resistor divider has a 10:1 ratio, the output voltage

profile will be able to vary from 1 V to 25.5 V with 100 mV

steps.

Table 4. VOLTAGE PROFILE SETTINGS

VPS_7 VPS_6 VPS_5 VPS_4 VPS_3 VPS_2 VPS_1 VPS_0

Voltage Profile

Hex Value

Reference

Voltage (mV)

0 0 0 0 0 0 0 0 00H 0

0 0 0 0 0 0 0 1 01H 10

0 0 0 0 0 0 1 0 02H 20

… … … … … … … … … …

0 0 1 1 0 0 1 0 32H 500 (Default)

… … … … … … … … … …

1 1 0 0 0 1 1 1 C7H 1990

1 1 0 0 1 0 0 0 C8H 2000

1 1 1 1 1 1 1 1 FFH 2550

Transconductance Voltage Error Amplifier

To maintain loop stability under a large change in

capacitance, the NCP81239 can change the gm of the

internal transconductance error amplifier from 87 mS to

1000 mS allowing the DC gain of the system to be increased

more than a decade triggered by the adding and removal of

the bulk capacitance or in response to another user input.

The default transconductance is 500 mS.

Table 5. AVAILABLE TRANSCONDUCTANCE SETTING

AMP_2 AMP_1 AMP_0

Amplifier GM Value (mS)

0 0 0 87

0 0 1 100

0 1 0 117

0 1 1 333

1 0 0 400

1 0 1 500

1 1 0 667

1 1 1 1000

Programmable Slew Rate

The slew rate of the NCP81239 is controlled via the I

registers with the default slew rate set to 0.6 mV/ms

(FB = 0.1 V2, assume the resistor divider ratio is 10:1)

which is the slowest allowable rate change. The slew rate is

used when the output voltage starts from 0 V to a user

selected profile level, changing from one profile to another,

or when the output voltage is dynamically changed. The

output voltage is divided by a factor of the external resistor

divider and connected to FB pin. The 9 Bit DAC is used to

increase the reference voltage in 10 or 5 mV increments.

The slew rate is decreased by using a slower clock that

results in a longer time between voltage steps, and

conversely increases by using a faster clock. The step

monotonicity depends on the bandwidth of the converter

where a low bandwidth will result in a slower slew rate than

the selected value. The available slew rates are shown in

Table 6. The selected slew rate is maintained unless the

current limit is tripped; in which case the increased voltage

will be governed by the positive current limit until the output

voltage falls or the fault is cleared.

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Figure 5. Slew Rate Limiting Block Diagram and Waveforms

9 bit DAC

−

FB = 0.1*V2

DAC_TARGET

DAC_TARGET_LSB

VREF

2.56

Table 6. SLEW RATE SELECTION

Slew Bits

Soft Start or Voltage Transition

(FB = 0.1*V2)

Slew_0

0.61 mV/ms

Slew_1

1.2 mV/ms

Slew_2

2.4 mV/ms

Slew_3

4.9 mV/ms

The discharge slew rate is accomplished in much the same

way as the charging except the reference voltage is

decreased rather than increased. The slew rate is maintained

unless the negative current limit is reached. If the negative

current limit is reached, the output voltage is decreased at the

maximum rate allowed by the current limit (see the negative

current limit section).

Soft Start

During a 0 V soft start, standard converters can start in

synchronous mode and have a monotonic rising of output

voltage. If a prebias exists on the output and the converter

starts in synchronous mode, the prebias voltage could be

discharged. The NCP81239 controller ensures that if a

prebias is detected, the soft start is completed in a

non−synchronous mode to prevent the output from

discharging. During softstart, the output rising slew rate will

follow the slew rate register with default value set to

0.6 mV/ms (FB = 0.1*V2).

Frequency Programming

The switching frequency of the NCP81239 can be

programmed from 150 kHz to 1.2 MHz via the I

C interface.

The default switching frequency is set to 600 kHz. The

switching frequency can be changed on the fly. However, it

is a good practice to disable the part and then program to a

different frequency to avoid transition glitches at large load

current.

Table 7. FREQUENCY PROGRAMMING TABLE

Name Bit Definition Description

Freq1 03H [2:0] Frequency Setting 3 Bits that Control the Switching Frequency from 150 kHz to 1 MHz.

000: 600 kHz

001: 150 kHz

010: 300 kHz

011: 450 kHz

100: 750 kHz

101: 900 kHz

110: 1.2 MHz

111: Reserved

Current Sense Amplifiers

Internal precision differential amplifiers measure the

potential between the terminal CSP1 and CSN1 or CSP2 and

CSN2. Current flows from the input V1 to the output in a

buck boost design. Current flowing from V1 through the

switches to the inductor passes through R

SENSE

. The

external sense resistor, R

SENSE

, has a significant effect on

the function of current sensing and limiting systems and

must be chosen with care. First, the power dissipation in the

resistor should be considered. The system load current will

cause both heat and voltage loss in R

SENSE

. The power loss

and voltage drop drive the designer to make the sense

resistor as small as possible while still providing the input

dynamic range required by the measurement. Note that input

dynamic range is the difference between the maximum input

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signal and the minimum accurately measured signal, and is

limited primarily by input DC offset of the internal

amplifier. In addition, R

SENSE

must be small enough that

SENSE

does not exceed the maximum input voltage

100 mV, even under peak load conditions.

The potential difference between CSPx and CSNx is level

shifted from the high voltage domain to the low voltage

VCC domain where the signal is split into two paths.

The first path, or external path, allows the end user to

observe the analog or digital output of the high side current

sense. The external path gain is set by the end user allowing

the designer to control the observable voltage level. The

voltage at CS1 or CS2 can be converted to 7 bits by the ADC

and stored in the internal registers which are accessed

through the I

C interface.

The second path, or internal path, has internally set gain

of 10 and allows cycle by cycle precise limiting of positive

and negative peak input current limits.

Figure 6. Block Diagram and Typical Connection for Current Sense

CS2

ILOAD

Rsense

5 mW

−

CSN1/CSN2

CSP1/CSP2

CS2

CLIND

VCM

−

10X

−

Positive Current

Limit

Negative Current

Limit

CLIP

CLIN

VCC

Internal Path

CS1 or CS2

ADC

CS1

−

CS2 MUX

CS1 MUX

RAMP 1

RAMP 2

10x(CSP2-CSN2)

10x(CSP1-CSN1)

Positive Current Limit Internal Path

The NCP81239 has a pulse by pulse current limiting

function activated when a positive current limit triggers.

CSP1/CSN1 will be the positive current limit sense channel.

When a positive current limit is triggered, the current

pulse is truncated. In both buck mode and in boost mode the

S1 switch is turned off to limit the energy during an over

current event. The current limit is reset every switching

cycle and waits for the next positive current limit trigger. In

this way, current is limited on a pulse by pulse basis. Pulse

by pulse current limiting is advantageous for limiting energy

into a load in over current situations but are not up to the task

of limiting energy into a low impedance short. To address the

low impedance short, the NCP81239 does pulse by pulse

current limiting for 2 ms known as Ilim timeout or until the

output voltage falls below 300 mV, the controller will enter

into fast stop. The NCP81239 remains in fast stop state with

all switches driven off for 10 ms. Once the 10 ms has

expired, the part is allowed to soft start to the previously

programmed voltage and current level if the short circuit

condition is cleared.

The internal current limits can be controlled via the I

interface as shown in Table 8.

Table 8. INTERNAL PEAK CURRENT LIMIT

CLIN_1 CLIN_0 CLIM delta Value (mV) CSP2−CSN2 (mV)

Current at RSENSE = 5 mW (A)

0 0 −400 −40 (Default) −8

0 1 −250 −25 −5

1 0 −150 −15 −3

1 1 0 0 0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

NCP81239MNTXG

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Switching Controllers I2C CONFIGURABLE 4 SWITCH

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