NCP81239, NCP81239A
www.onsemi.com
14
Overvoltage Protection (OVP)
When the divided output voltage is 120% (typical) above
the internal reference voltage for greater than one switching
cycle, an OV fault is set. During an overvoltage fault, S1 is
driven off, S2 is driven on, and S3 and S4 are modulated to
discharge the output voltage while preventing the inductor
current from going beyond the I
2
C programmed negative
current limit.
Figure 7. Diagram for OV Protection
V1 V2
L1S1
S2
S4
S3
During overvoltage fault detection the switching
frequency changes from its I
2
C set value to 50 kHz to reduce
the power dissipation in the switches and prevent the
inductor from saturating. OOV is disabled during voltage
changes to ensure voltage changes and glitches during
slewing are not falsely reported as faults. The OOV faults
are reengaged 1 ms after completion of the soft start.
Figure 8. OV Block Diagram
−
+
VFB
OV_REF
OV
OV_MSK
Table 10. OVERVOLTAGE MASKING
OV_MSK Description
0 OV Action and Indication Unmasked
1 OV Action and Indication Masked
Power Good Monitor (PG)
NCP81239 provides two window comparators to monitor
the internal feedback voltage. The target voltage window is
±5% of the reference voltage (typical). Once the feedback
voltage is within the power good window, a power good
indication is asserted once a 3.3 ms timer has expired. If the
feedback voltage falls outside a ±7% window for greater
than 1 switching cycle, the power good register is reset.
Power good is indicated on the INT pin if the I
2
C register is
set to display the PG state. During startup, INT is set until the
feedback voltage is within the specified range for 3.3 ms.
Figure 9. PG Block Diagram
−
+
VFB
PG_Low
PG_High
−
+
PG
PG_MSK
Table 11. POWER GOOD MASKING
PG_MSK Description
0 PG Action and Indication Unmasked
1 PG Action and Indication Masked
Thermal Shutdown
The NCP81239 protects itself from overheating with an
internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown threshold
(typically 150°C), all MOSFETs will be driven to the off
state, and the part will wait until the temperature decreases
to an acceptable level. The fault will be reported to the fault
register and the INT flag will be set unless it is masked.
When the junction temperature drops below 125°C
(typical), the part will discharge the output voltage to Vsafe
0 V.
CFET Turn On
The CFET is used to engage the output bulk capacitance
after successful negotiations between a consumer and a
provider. The USB Power Delivery Specification requires
that no more than 30 mF of capacitance be present on the
VBUS rail when sinking power. Once the consumer and
provider have completed a power role swap, a larger
capacitance can be added to the output rail to accommodate
a higher power level. The bulk capacitance must be added in
such a way as to minimize current draw and reduce the
voltage perturbation of the bus voltage. The NCP81239
incorporates a right drive circuit that regulates current into
the gate of the MOSFET such that the MOSFET turns on
slowly reducing the drain to source resistance gradually.
Once the transition from high to low has occurred in a
controlled way, a strong pulldown driver is used to ensure
normal operation does not turn on the power N−MOSFET
engaging the bulk capacitance. The CFET must be activated
through the I
2
C interface where it can be engaged and
disengaged. The default state is to have the CFET
disengaged.
