LTM8001
9
8001fd
For more information www.linear.com/LTM8001
pin FuncTions
V
IN0
(Bank 1): The V
IN0
bank supplies current to the
LTM8001’s internal regulator and to the internal power
switches. This pin must be locally bypassed with an ex
-
ternal, low ESR capacitor; see Table 1 for recommended
values.
GND (Bank 2): Tie these GND pins to a local ground plane
below the LTM8001 and the circuit components. In most
applications, the bulk of the heat flow out of the LTM8001
is through these pads, so the printed circuit design has a
large impact on the thermal performance of the part. See
the PCB Layout and Thermal Considerations sections for
more details. Return the feedback divider (R
FB0
) to this net.
V
IN45
(Bank 3): Input to the LDOs connected to V
OUT4
and
V
OUT5
. It must be locally bypassed with a low ESR capacitor.
V
OUT0
(Bank 4): Switching Power Converter Output Pins.
Apply the output filter capacitor and the output load between
these pins and the GND pins. In most cases, an output
capacitance made up of a combination of ceramic and elec
-
trolytic capacitors yields the optimal volumetric solution.
BIAS45
(Pin A8): This pin is the supply pin for the control
circuitry of the LDOs connected to V
OUT4
and V
OUT5
. For
the LDOs to regulate, this voltage must be more than
1.2V to 1.6V greater than the output voltage (see Dropout
specifications).
BIAS123 (Pin B8): This pin is the supply pin for the
control circuitry of the LDOs connected to V
OUT1
-V
OUT3
.
For the LDOs to regulate, this voltage must be more than
1.2V to 1.6V greater than the output voltage (see Dropout
specifications).
SS (Pin K4): The Soft-Start Pin. Place an external capacitor
to ground to limit the regulated current during start-up
conditions. The soft-start pin has an 11μA charging current.
SYNC (Pin K7): Frequency Synchronization Pin. This pin
allows the switching frequency to be synchronized to
an external clock. The R
T
resistor should be chosen to
operate the internal clock at 20% slower than the SYNC
pulse frequency. This pin should be grounded when not
in use. Do not leave this pin floating. When laying out the
board, avoid noise coupling to or from the SYNC trace.
See the Switching Frequency Synchronization section in
Applications Information.
V
REF
(Pin K8): Buffered 2V Reference Capable of 0.5mA
Drive.
RUN (Pin L4): The RUN pin acts as an enable pin and
turns on the internal circuitry. The pin does not have any
pull up or pull down, requiring a voltage bias for normal
part operation. The RUN pin is internally clamped, so it
may be pulled up to a voltage source that is higher than
Typical perForMance characTerisTics
(T
A
= 25°C unless otherwise noted. Configured per Table 1, where applicable.)
LDO V
BIAS
Ripple Rejection
(V
OUT4
= 2.5V, V
BIAS45
= 4.5V,
V
IN45
= 3.5V) LDO Output Ripple
FREQUENCY (Hz)
10
RIPPLE REJECTION (dB)
60
80
100
8001 G38
40
20
50
70
90
30
10
0
10
2
10
3
10
4
10
5
10
6
I
LOAD
= 100mA
I
LOAD
= 1.1A
2µs/DIV
V
OUT
= 1.2V AT 700mA
C
OUT1
= 22µF
C
SET1
= 1nF
V
IN
= 12V
V
OUT0
= 1.8V LOADED TO
A TOTAL CURRENT OF 5A
100MHz BW
8001 G39
1mV/DIV
