LTC3417A-1
13
3417a1fa
Soft-Start
Soft-start reduces surge currents from V
IN
by gradu-
ally increasing the peak inductor current. Power supply
sequencing can also be accomplished by controlling the
I
TH
pin. The LTC3417A-1 has an internal digital soft-start
for each regulator output, which steps up a clamp on
I
TH
over 1024 clock cycles, as can be seen in Figures 2
and 3. As the voltage on I
TH
ramps through its operating
range, the internal peak current limit is also ramped at a
proportional linear rate.
Mode Selection
The SYNC/MODE pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to V
IN
enables Burst Mode operation for both
regulators, which provides the best low current effi ciency
at the cost of a higher output voltage ripple. When SYNC/
MODE is connected to ground, pulse skipping operation
is selected for both regulators, which provides the low-
est output voltage and current ripple at the cost of low
current effi ciency. Applying a voltage that is more than
1V from either supply results in forced continuous mode
for both regulators, which creates a fi xed output ripple
and allows the sinking of some current (about 1/2ΔI
L
).
Since the switching noise is constant in this mode, it is
also the easiest to fi lter out. In many cases, the output
voltage can be simply connected to the SYNC/MODE pin,
selecting the forced continuous mode except at start-up.
The LTC3417A-1 can be synchronized to an external clock
signal by the SYNC/MODE pin. The internal oscillator fre-
quency should be set to 20% lower than the external clock
frequency to ensure adequate slope compensation, since
slope compensation is derived from the internal oscillator.
During synchronization, the mode is set to pulse skipping
and the top switch turn-on is synchronized to the rising
edge of the external clock.
When using an external clock, with the PHASE pin low, the
switching of the two channels occur at the edges of the
external clock. A 50% duty cycle will therefore produce
180° out-of-phase operation.
Checking Transient Response
The I
TH
pin compensation allows the transient response
to be optimized for a wide range of loads and output
capacitors. The availability of the I
TH
pin not only allows
optimization of the control loop behavior, but also pro-
vides a DC coupled and AC fi lited closed-loop response
test point. The DC step, rise time, and settling at this test
point truly refl ects the closed-loop response. Assuming a
predominantly second order system, phase margin and/or
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated using the percentage of overshoot seen at this
pin or by examining the rise time at this pin.
APPLICATIONS INFORMATION
V
IN
= 3.6V
V
OUT
= 1.8V
R
L
= 0.9Ω
200µs/DIV
I
L
1A/DIV
V
OUT
1V/DIV
V
RUN
2V/DIV
3417A-1 F02
Figure 2. Digital Soft-Start OUT1
V
IN
= 3.6V
V
OUT
= 2.5V
R
L
= 2Ω
200µs/DIV
I
L
0.5A/DIV
V
OUT
1V/DIV
V
RUN
2V/DIV
3417A-1 F03
Figure 3. Digital Soft-Start OUT2
LTC3417A-1
14
3417a1fa
The I
TH
external components shown in the Figure 4 circuit
will provide an adequate starting point for most applica-
tions. The series RC fi lter sets the dominant pole-zero
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because of various types and values determine the loop
feedback factor gain and phase. An output current pulse
of 20% to 100% of full load current having a rise time
of 1µs to 10µs will produce output voltage and I
TH
pin
waveforms that will give a sense of overall loop stability
without breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
OUT
im-
mediately shifts by an amount equal to ΔI
LOAD
• ESR
COUT
,
where ESR
COUT
is the effective series resistance of C
OUT
.
ΔI
LOAD
also begins to charge or discharge C
OUT
generat-
ing a feedback error signal used by the regulator to return
V
OUT
to its steady-state value. During this recovery time,
V
OUT
can be monitored for overshoot or ringing that would
indicate a stability problem.
The initial output voltage step may not be within the band-
width of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. The gain of the loop increases with R
ITH
and the
bandwidth of the loop increases with decreasing C
ITH
. If
R
ITH
is increased by the same factor that C
ITH
is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, feedforward capacitors,
C1 and C2, can be added to improve the high frequency
response, as shown in Figure 4. Capacitor C1 provides
phase lead by creating a high frequency zero with R1
which improves the phase margin for the 1.5A SW1 chan-
nel. Capacitor C2 provides phase lead by creating a high
frequency zero with R3 which improves the phase margin
for the 1A SW2 channel.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage V
IN
drops toward V
OUT
, the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta, or single inductor, positive buck boost.
In some applications, a more severe transient can be
caused by switching in loads with large (>1µF) input ca-
pacitors. The discharged input capacitors are effectively
put in parallel with C
OUT
, causing a rapid drop in V
OUT
. No
regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot Swap™ controller
is designed specifi cally for this purpose and usually in-
corporates current limiting, short-circuit protection, and
soft- starting.
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
% Effi ciency = 100% – (P1+ P2 + P3 +…)
where P1, P2, etc. are the individual losses as a percent-
age of input power.
Hot Swap is a trademark of Linear Technology Corporation.
APPLICATIONS INFORMATION
LTC3417A-1
15
3417a1fa
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses
in LTC3417A-1 circuits: 1) LTC3417A-1 I
S
current, 2)
switching losses, 3) I
2
R losses, 4) other losses.
1) The I
S
current is the DC supply current given in the elec-
trical characteristics which excludes MOSFET driver and
control currents. I
S
current results in a small (<0.1%)
loss that increases with V
IN
, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge moves from
V
IN
to ground. The resulting charge over the switching
period is a current out of V
IN
that is typically much larger
than the DC bias current. The gate charge losses are
proportional to V
IN
and thus their effects will be more
pronounced at higher supply voltages.
3) I
2
R losses are calculated from the DC resistances of the
internal switches, R
SW
, and the external inductor, R
L
. In
continuous mode, the average output current fl owing
through inductor L is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET R
DS(ON)
and the duty cycle (DC) as
follows:
R
SW
= (R
DS(ON)
TOP)(DC) + (R
DS(ON)
BOT)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2
(R
SW
+ R
L
)
where R
L
is the resistance of the inductor.
4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional effi ciency
degradations in portable systems. It is very important
to include these “system” level losses in the design
of a system. The internal battery and fuse resistance
losses can be minimized by making sure that C
IN
has
adequate charge storage and very low ESR
COUT
at
the switching frequency. Other losses including diode
conduction losses during dead-time and inductor core
losses generally account for less than 2% total additional
loss.
Thermal Considerations
The LTC3417A-1 requires the package Exposed Pad
(PGND2/GNDD pin) to be well soldered to the PC board.
This gives the DFN and TSSOP packages exceptional
thermal properties, compared to similar packages of this
size, making it diffi cult in normal operation to exceed the
maximum junction temperature of the part. In a majority
of applications, the LTC3417A-1 does not dissipate much
heat due to its high effi ciency. However, in applications
where the LTC3417A-1 is running at high ambient tem-
perature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both switches
in both regulators will be turned off and the SW nodes will
become high impedance.
To prevent the LTC3417A-1 from exceeding its maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
RISE
= P
D
θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
RISE
+ T
AMBIENT
As an example, consider the case when the LTC3417A-1
is in dropout in both regulators at an input voltage of 3.3V
with load currents of 1.5A and 1A. From the Typical Per-
formance Characteristics graph of Switch Resistance, the
R
DS(ON)
resistance of the 1.5A P-channel switch is 0.09
and the R
DS(ON)
of the 1A P-channel switch is 0.163.
APPLICATIONS INFORMATION

LTC3417AEFE-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual 1.5A & 1A, 4MHz Synchronous Step-Down DC/DC Converter in 3x5 DFN-16 or TSSOP-20E
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union