LTC3417A-1
16
3417a1fa
The power dissipated by the part is:
PD = I
1
2
• R
DS(ON)1
+ I
2
2
• R
DS(ON)2
PD = 1.5
2
• 0.09 + 1
2
• 0.163
PD = 366mW
The DFN package junction-to-ambient thermal resistance,
θ
JA
, is about 43°C/W. Therefore, the junction temperature
of the regulator operating in a 70°C ambient temperature
is approximately:
T
J
= 0.366 • 43 + 70
T
J
= 85.7°C
Remembering that the above junction temperature is
obtained from an R
DS(ON)
at 25°C, we might recalculate
the junction temperature based on a higher R
DS(ON)
since
it increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
Design Example
As a design example, consider using the LTC3417A-1 in
a portable application with a Li-Ion battery. The battery
provides a V
IN
from 2.8V to 4.2V. One load requires 1.8V
at 1.5A in active mode, and 1mA in standby mode. The
other load requires 2.5V at 1A in active mode, and 500µA
in standby mode. Since both loads still need power in
standby, Burst Mode operation is selected for good low
load effi ciency (SYNC/MODE = V
IN
).
First, determine what frequency should be used. Higher
frequency results in a lower inductor value for a given ΔI
L
(ΔI
L
is estimated as 0.35I
LOAD(MAX)
). Reasonable values
for wire wound surface mount inductors are usually in the
range of 1µH to 10µH.
Using the 1.5MHz frequency setting (FREQ = V
IN
), we get
the following equations for L1 and L2:
L1=
1.8V
1.5MHz 525mA
1–
1.8V
4.2V
= 1.3μH
Use 1.5μH.
L2=
2.5V
1.5MHz 350m
A
1–
2.5V
4.2V
= 1.9μH
Use 2.2μH.
C
OUT
selection is based on load step droop instead of ESR
requirements. For a 2.5% output droop:
C
OUT1
= 2.5
1.5A
1.5MHz 5% 1.8V
()
= 28μF
C
OUT2
= 2.5
1A
1.5MHz 5% 2.5V
()
= 13μF
The closest standard values are 47µF and 22µF.
The output voltages can now be programmed by choos-
ing the values of R1, R2, R3, and R4. To maintain high
effi ciency, the current in these resistors should be kept
small. Choosing 2µA with the 0.8V feedback voltages makes
R2 and R4 equal to 400k. A close standard 1% resistor is
412k. This then makes R1 = 515k. A close standard 1%
is 511k. Similarily, with R4 at 412k, R3 is equal to 875k.
A close 1% resistor is 866k.
The compensation should be optimized for these compo-
nents by examining the load step response, but a good
place to start for the LTC3417A-1 is with a 5.9k and
2200pF fi lter on I
TH1
and 2.87k and 6800pF on I
TH2
. The
output capacitor may need to be increased depending on
the actual undershoot during a load step.
The POR pin is an open drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.
Figure 4 shows a complete schematic for this design.
CONVERTER OUTPUT I
LOAD(MAX)
ΔI
L
SW1 1.5A 525mA
SW2 1A 350mA
APPLICATIONS INFORMATION
LTC3417A-1
17
3417a1fa
Figure 4. 1.8V at 1.5A/2.5V at 1A Step-Down Regulators
OUT1 Effi ciency vs Load Current
SYNC/MODE
SW1
RUN1
V
FB1
PHASE
I
TH1
POR
SW2
RUN2
V
FB2
FREQ
I
TH2
V
IN1
LTC3417A-1
GNDA
EXPOSED
PAD GNDD
V
IN2
C
IN
10µF
C
IN1
0.1µF
C
IN2
0.1µF
L1
1.5µH
L2
2.2µH
C1 22pF
R1 511k
C2 22pF
R3 866k
V
IN
V
IN
V
IN
R7
100k
R2
412k
R4
412k
C
OUT2
22µF
R5
5.9k
R6
2.87k
C3
2200pF
C4
6800pF
3417A-1 F04
C
OUT1
47µF
V
OUT1
1.8V
1.5A
V
OUT2
2.5V
1A
V
IN
2.25V TO 5.5V
L1: MIDCOM DUS-5121-1R5R
C
OUT1
: KEMET C1210C226K8PAC
L2: MIDCOM DUS-5121-2R2R
C
OUT2
, C
IN
: KEMET C1206C106K4PAC
RESET
LOAD CURRENT (A)
80
EFFICIENCY (%)
POWER LOSS (W)
90
100
75
85
95
0.001 0.1 1 10
3417A-1 F04a
70
0.1
10
0.01
1
0.001
0.01
EFFICIENCY
POWER LOSS
V
IN
= 3.6V
V
OUT
= 1.8V
FREQ = 1MHz
REFER TO FIGURE 4
APPLICATIONS INFORMATION
LTC3417A-1
18
3417a1fa
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3417A-1. These items are also illustrated graphically
in the layout diagram of Figure 5. Check the following in
your layout.
1
. Does the capacitor C
IN
connect to the power V
IN1
(Pin 2), V
IN2
(Pin 8), and PGND2/GNDD (Pin 17) as
close as possible (DFN package)? It may be necessary
to split C
IN
into two capacitors. This capacitor provides
the AC current to the internal power MOSFETs and
their drivers.
2. Are the C
OUT1
, L
1
and C
OUT2
, L
2
closely connected? The
(–) plate of C
OUT1
returns current to PGND1, and the
(–) plate of C
OUT2
returns current to the
PGND2/GNDD
and the (–) plate of C
IN
.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
OUT1
and a ground line ter-
minated near GNDA. The resistor divider, R3 and R4,
must be connected between the (+) plate of C
OUT2
and
a ground line terminated near GNDA. The feedback
signals V
FB1
and V
FB2
should be routed away from noise
components and traces, such as the SW lines, and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor C
IN
, the compensation capacitors
C
C1
, C
C2
, C
ITH1
and C
ITH2
and all resistors R1, R2, R3,
R4, R
ITH1
and R
ITH2
should be routed away from the
SW traces and the inductors L1 and L2.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GNDA pin at one
point which is then connected to the
PGND2/GNDD
pin.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to one of the input supplies.
Figure 5. Layout Guideline
V
IN2
PGND2/
EXPOSED PAD
V
IN1
PGND1
SW1
V
FB1
I
TH1
FREQ
RUN1
SYNC/MODE
LTC3417A-1
GNDD
V
IN
V
IN
V
IN
C
IN
10µF
C
IN2
0.1µF
C
IN1
0.1µF
C
OUT2
V
OUT2
C
OUT1
V
OUT1
L2 L1
C
C2
C
C1
R3
R4
R
ITH2
C
ITH2
C
ITH1
R8
R1
R2
R
ITH1
R7
STAR TO
GNDA
STAR TO
GNDA
GNDA
SW2
V
FB2
I
TH2
POR
RUN2
PHASE
3417A-1 F05
APPLICATIONS INFORMATION

LTC3417AEFE-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual 1.5A & 1A, 4MHz Synchronous Step-Down DC/DC Converter in 3x5 DFN-16 or TSSOP-20E
Lifecycle:
New from this manufacturer.
Delivery:
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