AD8309ARUZ Datasheet AD8309ARUZ, AD8309ARU, AD8309ARU-REEL7 | P10-P12

REV. B

AD8309

–10–

sensitivity to disturbances on the supply lines. With careful

design, the sensitivities to many other parametric variations, and

the effects of temperature and supply voltage, can be reduced to

negligible proportions.

A/0 A/0 A/0

STAGE 1 STAGE 2 STAGE N

–

SLOPE

LOG

LIM

+TOP-END

DETECTORS

CURRENT-SUMMING LINE

Figure 24. Basic Log Amp Structure Using A/0 Stages and

Transconductance (g

) Cells for Summing

The output of each gain cell has an associated transconductance

) cell, which converts the differential output voltage of the

cell to a pair of differential currents; these are summed by sim-

ply connecting the outputs of all the g

(detector) stages in

parallel. The total current is then converted back to a voltage by

a transresistance stage, which determines the slope of the loga-

rithmic output. This general scheme is depicted, in a simplified

single-sided form, in Figure 24. Additional detectors, driven by

a passive attenuator, may be added to extend the top end of the

dynamic range.

The slope voltage may now be decoupled from the knee-voltage

= 2kT/q, which is inherently PTAT. The detector stages are

biased with currents (not shown in the Figure) which can be

derived from a band-gap reference and thus be stable with tem-

perature. This is the architecture used in the AD8309. It affords

complete control over the magnitude and temperature behavior

of the logarithmic slope.

A further step is yet needed to achieve the demodulation response,

required in a log-limiter amp is to convert an alternating input

into a quasi- dc baseband output. This is achieved by modifying

the g

cells used for summation purposes to implement the

rectification function. Early log amps based on the progressive

compression technique used half-wave rectifiers, which made

post-detection filtering difficult. The AD640 was the first com-

mercial monolithic log amp to use a full-wave rectifier; this

proprietary practice has been used in all subsequent Analog

Devices types.

We can model these detectors as being essentially linear g

cells,

but producing an output current that is independent of the sign

of the voltage applied to the input. That is, they implement the

absolute-value function. Since the output from the later A/0 stages

closely approximates an amplitude symmetric square wave for

even moderate input levels, the current output from each detec-

tor is almost constant over each period of the input. Somewhat

earlier detectors stages in the chain produce a waveform having

only very brief “dropouts” at twice the input frequency. Only

those detectors nearest the log amp’s input produce a low level

waveform that is approximately sinusoidal. When all these (cur-

rent mode) outputs are summed, the resulting signal has a wave-

form which is readily filtered, to provide a low residual ripple on

the output.

Intercept Calibration

Monolithic log amps from Analog Devices incorporate accurate

means to position the intercept voltage V

(or equivalent sine-

wave power for a demodulating log amp, when driven at a spe-

cific impedance level). Using the scheme shown in Figure 24,

the value of the intercept level departs considerably from that

predicted by the simple theory. Nevertheless, the intrinsic inter-

cept voltage is still proportional to E

, which is PTAT (propor-

tional to absolute temperature).

Recalling that the addition of an offset to the output produces

an effect which is indistinguishable from a change in the posi-

tion of the intercept, it will be apparent that we can cancel the

“left-right” motion of V

resulting from the temperature varia-

tion of E

by simply adding an offset at its demodulated output

having the required temperature behavior.

The precise temperature-shaping of the intercept-positioning

offset can result in a log amp having stable scaling parameters,

making it a true measurement device, for example, as a calibrated

Received Signal Strength Indicator (RSSI). In this application,

one is more interested in the value of the output for an input

waveform which is often sinusoidal (CW). The input level be

stated as an equivalent power, in dBm, but it is essential to

know the impedance level at which this “power” is presumed to

be measured. In an impedance of 50 Ω, 0 dBm (1 mW) corre-

sponds to a sinusoidal amplitude of 316.2 mV (223.6 mV rms).

For the AD8309, the intercept may be specified in dBm when

the input impedance is lowered to 50 Ω, by the addition of a

shunt resistor of 52.3 Ω, in which case it occurs at –95 dBm.

However, the response is actually to the voltage at the input, not

the power in the termination resistor, and should be specified in

dBV. A –95 dBm sine input across a 50 Ω resistance corre-

sponds to an amplitude of 5.6 µV, or –108 dBV, where 0 dBV is

specified as a sine waveform of 1 V rms, that is, 2.8 V p-p.

Note that a log amp’s intercept is a function of waveform. For

example, a square-wave input will read 6 dB

higher than a sine-

wave of the same amplitude, and a Gaussian noise input 0.5 dB

higher than a sine wave of the same rms value. Further, a log

amp driven by the sum of two sinusoidal voltages of equal am-

plitude will show an output that is only 2.1 dB higher than the

response for a single sine wave drive, rather than the 3 dB that

might be expected if the device truly responded to input power.

These are characteristics exhibited by all demodulating log amps.

Dynamic Range

The lower end of the dynamic range is determined largely by the

thermal noise floor, measured at the input of the amplifier chain.

For the AD8309, the short-circuit input-referred noise-spectral

density is 1.1 nV/√Hz, and 1.275 nV/√Hz when driven from a

net source impedance of 25 Ω (a terminated 50 Ω). This corre-

sponds to a noise power of –78 dBm in a 500 MHz bandwidth.

The upper end of the dynamic range is extended upward by the

addition of top-end detectors driven by a tapped attenuator. These

smaller signals are applied to additional full-wave detectors

whose outputs are summed with those of the main detectors.

With care in design, this extension in the dynamic range can be

‘seamless’ over the full frequency range. For the AD8309 it

amounts to a further 48 dB. When using a supply of 4.5 V or

greater, an input amplitude of 4 V can be accommodated, corre-

sponding to a power level of +22 dBm in 50 Ω. (A larger input

voltage may cause damage.)

REV. B

AD8309

–11–

The total dynamic range of the AD8309, defined as the ratio

of the maximum permissible input to the noise floor, is thus

100 dB. Good accuracy is provided over a substantial part of

this range.

Input Matching

Monolithic log amps present a nominal input impedance much

higher than 50 Ω. For the AD8309, this can be modeled as 1 kΩ

shunted by 2.5 pF, at frequencies up to 300 MHz. Thus, a

simple input matching network can considerably improve the

basic sensitivity , when driving from a low-impedance source, by

increasing the voltage applied to the input. For a 50:1000 Ω

transformation, the voltage gain is 13 dB, and the whole dy-

namic range moves downward by this amount; that is, the inter-

cept is shifted to –121 dBV (–108 dBm at the primary 50 Ω

input). Note that while useful voltage gain is achieved in this

way, it does not follow that the noise-figure is minimal at the

optimum power match.

Offset Control

In a monolithic log amp, direct-coupling between the stages is

invariably utilized for practical reasons. Now, a dc offset voltage

in the early stages of the chain is indistinguishable from a “real”

signal. If as high as 400 µV, it would be 20 dB larger than the

smallest resolvable ac signal (40 µV), reducing the dynamic

range by this amount. This problem is solved by using a global

feedback path from the last stage to the first. The high-frequency

components of the signal must be removed; this achieved in the

AD8309 by an on-chip low-pass filter, providing sufficient sup-

pression of HF feedback to allow accurate operation down to at

least 5 MHz. Useful operation at lower frequencies remains

possible, although a particular device having a large dc offset will

exhibit a reduction in the low end region of the dynamic range.

PRODUCT OVERVIEW

The AD8309 is built on an advanced dielectrically-isolated

complementary bipolar process using thin-film resistor technol-

ogy for accurate scaling. It follows well-developed foundations

proven over a period of some fifteen years, with constant refine-

ment. The backbone of the AD8309 (Figure 25) comprises a

chain of six main amplifier/limiter stages, each having a gain of

12.04 dB (×4) and small-signal –3 dB bandwidth of 850 MHz.

The input interface at INHI and INLO (Pins 4 and 5) is fully

differential. Thus it may be driven from either single-sided or

balanced inputs, the latter being required at the very top end of

the dynamic range, where the total differential drive may be as

large as 4 V in amplitude.

The first six stages, also used in developing the logarithmic

RSSI output, are followed by a versatile programmable output,

and thus programmable gain, final limiter section. Its open-

collector outputs are also fully differential, at LMHI and LMLO

(Pins 12 and 13). This output stage provides a gain of 18 dB

when using equal valued load and bias setting resistors and the

pin-to-pin output is used. The overall voltage gain is thus 100 dB.

When using R

LIM

= R

LOAD

= 200 Ω, the additional current

consumption in the limiter is approximately 2.8 mA, of which

2 mA goes to the load. The ratio depends on R

LIM

(for example,

when 20 Ω, the efficiency is 90%), and the voltage at the pin

LMDR is rather more than 400 mV, but the total load current is

accurately (400 mV)/R

LIM

The rise and fall times of the hard-limited (essentially square-

wave) voltage at the outputs are typically 0.4 ns, when driven by

a sine wave input having an amplitude of 100 mV or greater,

and R

LOAD

= 50 Ω. The change in time-delay (“phase skew”)

over the input range –83 dBV (100 mV in amplitude, or –70 dBm

in 50 Ω) to –3 dBV (1 V or +10 dBm) is ±83 ps (±3° at 100 MHz).

12dB LIM

DET

12dB

DET DET4 3 DET

LADR ATTEN

INHI

INLO

I-V

BIAS

CTRL

TEN DETECTORS SPACED 12dB

INTERCEPT

TEMP COMP

BAND-GAP

REFERENCE

ENBL

GAIN

BIAS

LMHI

LMLO

LMDR

VLOG

FLTR

SIX STAGES TOTAL GAIN 72dB TYP GAIN 18dB

SLOPE

BIAS

12dB

Figure 25. Main Features of the AD8309

The six main cells and their associated full-wave detectors,

having a transconductance (g

) form, handle the lower part of

the dynamic range. Biasing for these cells is provided by two

references, one of which determines their gain, the other being a

band-gap cell which determines the logarithmic slope, and stabi-

lizes it against supply and temperature variations. A special dc-

offset-sensing cell (not shown in Figure 25) is placed at the end

of this main section, and used to null any residual offset at the

input, ensuring accurate response down to the noise floor. The

first amplifier stage provides a short-circuited voltage-noise

spectral-density of 1.07 nV/√Hz.

The last detector stage includes a modification to temperature-

stabilize the log-intercept, which is accurately positioned so as to

make optimal use of the full output voltage range. Four further

“top end” detectors are placed at 12.04 dB taps along a passive

attenuator, to handle the upper part of the range. The differen-

tial current-mode outputs of all ten detectors stages are summed

with equal weightings and converted to a single-sided voltage by

the output stage, generating the logarithmic (or RSSI) output at

VLOG (Pin 16), nominally scaled 20 mV/dB (that is, 400 mV

per decade). The junction between the lower and upper regions

is seamless, and the logarithmic law-conformance is typically

well within ±0.4 dB from –83 dBV to +7 dBV (–70 dBm to

+10 dBm).

The full-scale rise time of the RSSI output stage, which operates

as a two-pole low-pass filter with a corner frequency of 3.5 MHz, is

about 200 ns. A capacitor connected between FLTR (Pin 10)

and VLOG can be used to lower the corner frequency (see be-

low). The output has a minimum level of about 0.34 V (corre-

sponding to a noise power of –78 dBm, or 17 dB above the

nominal intercept of –95 dBm). This rather high baseline level

ensures that the pulse response remains unimpaired at very low

inputs.

The maximum RSSI output depends on the supply voltage and

the load. An output of 2.34 V, that is, 20 mV/dB × (12 + 105) dB,

is guaranteed when using a supply voltage of 4.5 V or greater

and a load resistance of 50 Ω or higher, for a differential input

of 9 dBV (a 4 V sine amplitude, using balanced drives). When

using a 3 V supply, the maximum differential input may still be

as high as –3 dBV (1 V sine amplitude), and the corresponding

RSSI output of 2.1 V, that is, 20 mV/dB × (0 + 105) dB is also

guaranteed.

REV. B

AD8309

–12–

A fully-programmable output interface is provided for the hard-

limited signal, permitting the user to establish the optimal output

current from its differential current-mode output. Its magnitude

is determined by the resistor R

LIM

placed between LMDR (Pin

9) and ground, across which a nominal bias voltage of ~400 mV

appears. Using R

LIM

= 200 Ω, this dc bias current, which is

commutated alternately to the output pins, LMHI and LMLO,

by the signal, is 2 mA. (The total supply current is somewhat

higher).

These currents may readily be converted to voltage form by the

inclusion of load resistors, which will typically range from a few

tens of ohms at 500 MHz to as high as 2 kΩ in lower frequency

applications. Alternatively, a resonant load may be used to ex-

tract the fundamental signal and modulation sidebands, mini-

mizing the out-of-band noise. A transformer or impedance

matching network may also be used at this output. The peak

voltage swing down from the supply voltage may be 1.2 V, be-

fore the output transistors go into saturation. (The Applications

section provides further information on the use of this interface).

The supply current for all sections except the limiter output

stage, and with no load attached to the RSSI output, is nomi-

nally 16 mA at T

= 27°C, substantially independent of supply

voltage. It varies in direct proportion to the absolute tempera-

ture (PTAT). The RSSI load current is simply the voltage at

VLOG divided by the load resistance (e.g., 2.4 mA max in a

1 kΩ load). The limiter supply current is 1.1 times that flowing

in R

LIM

. The AD8309 may be enabled/disabled by a CMOS-

compatible level at ENBL (Pin 8).

In the following simplified interface diagrams, the components

denoted with an uppercase “R” are thin-film resistors having a

very low temperature-coefficient of resistance and high linearity

under large-signal conditions. Their absolute value is typically

within ±20%. Capacitors denoted using an uppercase “C” have

a typical tolerance of ±15% and essentially zero temperature or

voltage sensitivity. Most interfaces have additional small junc-

tion capacitances associated with them, due to active devices or

ESD protection; these may be neither accurate nor stable. Com-

ponent numbering in each of these interface diagrams is local.

Enable Interface

The chip-enable interface is shown in Figure 26. The current in

R1 controls the turn-on and turn-off states of the band-gap

reference and the bias generator, and is a maximum of 100 µA

when Pin 8 is taken to 5 V. Left unconnected, or at any voltage

below 1 V, the AD8309 will be disabled, when it consumes a

sleep current of much less than 1 µA (leakage currents only); when

tied to the supply, or any voltage above 2 V, it will be fully en-

abled. The internal bias circuitry requires approximately 300 ns

for either OFF or ON, while a delay of some 6 µs is required for

the supply current to fall below 10 µA.

1.3kV

50kV 4kV

COMM

ENBL

60kV

TO BIAS

ENABLE

Figure 26. Enable Interface

Input Interface

Figure 27 shows the essentials of the signal input interface. The

parasitic capacitances to ground are labeled C

; the differential

input capacitance, C

, mainly due to the diffusion capacitance

of Q1 and Q2. In most applications both input pins are ac-

coupled. The switch S closes when Enable is asserted. When

disabled, the inputs float, bias current I

is shut off, and the

coupling capacitors remain charged. If the log amp is disabled

for long periods, small leakage currents will discharge these

capacitors. If they are poorly matched, charging currents at

power-up can generate a transient input voltage which may

block the lower reaches of the dynamic range until it has be-

come much less than the signal.

In most applications, the input signal will be single-sided, and

may be applied to either Pin 4 or 5, with the remaining pin ac-

coupled to ground. Under these conditions, the largest input

signal that can be handled is –3 dBV (sine amplitude of 1 V)

when operating from a 3 V supply ; a +3 dBV input may be

handled using a supply of 4.5 V or greater. When using a fully-

balanced drive, the +3 dBV level may be achieved for the sup-

plies down to 2.7 V and +9 dBV using >4.5 V. For frequencies

in the range 10 MHz to 200 MHz these high drive levels are

easily achieved using a matching network (see later). Using such

a network, having an inductor at the input, the input transient is

eliminated.

= 1kV

SIGNAL

INPUT

INLO

INHI

VPS1

COMM

1.78V

3.65kV 3.65kV

1.725V

2.5pF

= 15mA

(TOP-END

DETECTORS)

2.6kV

= 3kV

20e

130V

3.4mA

PTAT

GAIN BIAS

1.26V

67V67V

TO STAGES

1 THRU 5

TO 2ND

STAGE

Figure 27. Signal Input Interface

Limiter Output Interface

The simplified limiter output stage is shown in Figure 28. The

bias for this stage is provided by a temperature-stable reference

voltage of nominally 400 mV which is forced across the external

resistor R

LIM

connected from Pin 9 (LMDR, or limiter drive) by

a special op amp buffer stage. The biasing scheme also intro-

duces a slight “lift” to this voltage to compensate for the finite

current gain of the current source Q3 and the output transistors

Q1 and Q2. A maximum current of 10 mA is permissible (R

LIM

= 40 Ω). In special applications, it may be desirable to modulate

the bias current; an example of this is provided in the Applica-

tions section. Note that while the bias currents are temperature

stable, the ac gain of this stage will vary with temperature, by

–6 dB over a 120°C range.

A pair of supply and temperature stable complementary currents

is generated at the differential output LMHI and LMLO (Pins

12 and 13), having a square wave form with rise and fall times

of typically 0.4 ns, when load resistors of 50 Ω are used. The

voltage at these output pins may swing to 1.2 V below the sup-

ply voltage applied to VPS2 (Pin 15).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

AD8309ARUZ

Mfr. #:

Buy AD8309ARUZ

Manufacturer:

Analog Devices Inc.

Description:

Logarithmic Amplifiers 5-500 MHz 100 dB w/ Limiter Output

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD8309ARUZ

AD8309ARUZ

Products related to this Datasheet